BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic depiction of a cross-section of a semiconductor wafer during one phase of manufacturing in accordance with embodiments of the present invention.
FIG. 2 shows the structure of FIG. 1 following planarization to expose the top portion of the gate electrode in accordance with embodiments of the present invention.
FIG. 3 depicts the structure of FIG. 2 after silicon is grown at the top portion of the gate electrode in accordance with embodiments of the present invention.
FIG. 4 shows the structure of FIG. 3 following etching to create offset spacers in accordance with embodiments of the present invention.
FIG. 5 depicts the structure of FIG. 3 following the deposition of a blocking dielectric layer in accordance with other embodiments of the present invention.
FIG. 6 shows the structure of FIG. 5 following the patterning of an offset and etching of the blocking dielectric layer in accordance with embodiments with the present invention.
FIG. 7 shows the structure of FIG. 6 after silicon is grown on the top portion of the gate electrode in accordance with embodiments of the present invention.
FIG. 8 depicts the structure of FIG. 7 following the removal of the blocking dielectric layer and etching of the dielectric layer to form differential offset spacers in accordance with embodiments of the present invention.
FIG. 9 depicts another embodiment of the present invention in which offset spacers of different widths are created in a microloading regime in accordance with embodiments of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention addresses and solves problems related to the formation of offset spacers and differential offset spacers by production-worthy methods, as well providing for offset spacers of different width for features having different CDs on the same wafer. This is achieved, at least in part, by the present invention which provides for exposing the top portion of a gate electrode from a dielectric layer. A selective epitaxial growth process is performed to create a silicon mask at the top of the gate electrode. The silicon mask overhangs the sidewalls of the gate electrode. Anisotropic etching is performed, the overhang of the silicon mask serving to mask the dielectric layer directly underneath the overhang. The protected portion of the dielectric layer forms the offset spacers on the sidewalls of the gate electrode. The invention also allows for forming differential offset spacers by the use of a blocking dielectric layer. In certain embodiments, the offset spacer deposition or etching is run in a strong microloading regime in order to provide wider offset spacers where the polysilicon CD is smaller, thereby resulting in improved Vt roll-off.
FIG. 1 is a schematic depiction of a cross-section of a portion of a semiconductor wafer during one phase of manufacture in accordance with embodiments of the present invention. A substrate 10, which may be a bulk silicon substrate, or silicon-on-insulator (SOI), strained silicon, etc., is provided. A silicon or polysilicon gate electrode 12 that is formed by conventional techniques such as deposition of a polysilicon layer and etching of the layer, is provided on the substrate 10. A dielectric layer 14 is deposited by conventional blanket deposition, for example, over the substrate 10 and the gate electrode 12. Dielectric layer 14 is made of material that will ultimately form the offset spacers. Hence, the dielectric layer 14 should be made of a material suitable for use as offset spacers, such as silicon oxide, silicon nitride, etc.
FIG. 2 shows the structure of FIG. 1 following a planarization that exposes the top portion 16 of the gate electrode 12. Planarization removes some of the dielectric layer 14 and creates a top surface 18 that is below the level of the polysilicon gate electrode 12. Planarization may be performed by a conventional technique, such as chemical mechanical polishing, for example.
Silicon is added, as depicted in FIG. 3, at the top portion of 16 of the gate electrode 12. The added silicon forms a silicon mask 20, as will become more apparent. In certain embodiments of the invention, the silicon mask 20 is formed by a selective epitaxial growth process by which silicon is grown at the top portion 16 of the gate electrode 12. It is assumed that the selective epitaxial growth of the silicon 20 creates symmetrical width overhangs 22 on each side of the gate electrode 12. A conventional selective epitaxial growth process may be performed to create the silicon mask 20.
After the silicon mask 20 has been created, an etching process is performed to create offset spacers 24 from the dielectric layer 14, as depicted in FIG. 4. The etch may be an anisotropic etch, for example, such as a reactive ion etch. A suitable etch chemistry is selected depending upon the material in the dielectric layer 14. For example, the etch chemistry should be such that only dielectric layer 14 is etched anisotropically, and the silicon of the silicon mask 20 or the substrate 10 is not substantially etched.
The offset spacers 24 are therefore created as depicted in FIG. 4, in a production-worthy manner with a precisely defined width. Further processing in accordance with conventional device processing techniques may now be performed.
There are certain instances in which it is desirable to create offset spacers of different width, i.e., having asymmetrical widths. An embodiment of the method of the present invention that produces asymmetrical width offset spacers is depicted in FIGS. 5-8. In FIG. 5, which follows FIG. 3 in the process flow in this embodiment, a blocking dielectric layer 26 is formed by blanket deposition over the top portion 16 of the gate electrode 12 and the top surface 18 of the dielectric layer 14. Blocking dielectric layer 26 is preferably made of material different from material in dielectric layer 14 so as to allow for precise control of etching and stopping at the top surface 18 of the dielectric layer 14, as will be appreciated. However, it is also possible for the blocking dielectric layer 26 to made of the same material as dielectric layer 14 by precisely controlling the etch time to stop the etch at the top surface 18 of the dielectric layer 14, or by monitoring the thickness during the etch with an in-situ optical interferometric technique where this metrology is integrated into the hardware of the etch too.
Patterning and etching of the blocking dielectric layer 26 is now performed in accordance with embodiments of the present invention. The results of the patterning and etching is depicted in FIG. 6. As can be seen, the patterning is made with an offset with respect to the top portion 16 of the gate electrode 12. Hence, a first side portion 28 of the top surface portion 18 of the dielectric layer 14 that is exposed has a different width than a second side portion 30 of the top surface portion 18 of the dielectric layer 14 on the second side of the top portion 16 of the gate electrode 12. In the illustrated embodiment, the second side portion 30 is wider than the first side portion 28.
The masking and patterning can be any given width, such that certain devices may have asymmetrical offset spacers, while other devices may have symmetrical offset spacers. Furthermore, certain devices may be provided with wider offset spacers by this method, while other devices on the same wafer may be provided with narrower offset spacers.
In FIG. 7, silicon is added to form a silicon mask 32. In this case, the silicon mask 32 is off-centered with respect to the gate electrode 12.
In FIG. 8, an anisotropic etch is performed in the same manner as depicted earlier with respect to FIG. 4. In this embodiment, the blocking dielectric layer 26 that formed a mask is first removed by an appropriate etching technique, and the dielectric layer 14 is then etched in the manner described-earlier. The etching creates asymmetrical offset spacers 34, 36, as defined by the overhang of the silicon mask 32. With the asymmetrical offset spacers 34, 36 now created, further processing of the device may occur in the normal process flow.
In certain instances, it is desirable to provide wider offset spacers on smaller gates, and thereby reduce the contribution of across chip line width variation (ACLV) to Vt roll-off and chip IDDQ. The present invention provides this by utilizing strong microloading in the deposition, etch, or selective epitaxial growth processes to create the wider offset spacers, as depicted in FIG. 9, on smaller gates. Narrower offset spacers may be formed on the wider gates. Microloading refers to the measure of difference in etch rate for large and small sized features. As seen in FIG. 9, a gate electrode 40 having a first width is provided on the same substrate as a gate electrode 42 having a second width that is wider than the first width. When run in a strong microloading regime, the offset spacers 44 that are created at the first width gate electrode 40 have a first width that is wider than the second offset spacers created at the second width gate electrodes 42. The offset spacers may be created by utilizing strong microloading during the deposition, etch or selective epitaxial growth processes to create the wider offset spacers on the smaller gates and the narrow offset spacers on the wider gates.
Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only, and is not to be taken by of limitation, the scope of the present invention being limited only by the terms of the appended claims.
Patent Application
20080090368
