This application claims the benefit of Taiwan Patent Application No. 111120048 filed on May 30, 2022, entitled “METHOD FOR FORMING SEMICONDUCTOR STRUCTURE” which is hereby incorporated herein by reference.
The present disclosure relates to a method for forming a semiconductor structure, and in particular, it relates to the active regions of the semiconductor structure.
In order to increase DRAM density and improve its performance, existing technologies for fabricating DRAM devices continue focusing on scaling down the DRAM's size.
The method of forming a semiconductor structure includes forming strip patterns over a semiconductor substrate, and forming a patterned mask layer over the strip patterns. The patterned mask layer includes first openings corresponding to the strip patterns. The first openings are arranged in an array in a first direction and a second direction. The second direction is perpendicular to the first direction. The first pitch of the first openings in the first direction is smaller than a second pitch of the first openings in the second direction. A first dimension of at least one of the first openings in the first direction is longer than a second dimension of the at least one of the first openings in the second direction. The method also includes forming spacers to partially fill the first openings, removing the patterned mask layer to form trenches between the spacers, forming a conformal layer to cover the spacers and partially fill the first openings and the trenches, and etching the strip patterns using the conformal layer and the spacers as a mask, thereby cutting the strip patterns into island patterns.
The method of forming a semiconductor structure includes forming first strip patterns over a semiconductor substrate, forming a hard mask layer over the first strip patterns, forming a photoresist material over the hard mask layer, and patterning the photoresist material using a photomask so that patterns of the photomask are transferred into the photoresist material to form a patterned photoresist material. At least one of the patterns of the photomask includes a body portion and an extending portion protruding from a side of the body portion. The patterned photoresist material has first openings corresponding to the first strip patterns. The method also includes forming spacers along sidewalls of the first openings, removing the patterned photoresist material, forming a conformal layer over the hard mask layer and along the spacers, and sequentially etching the hard mask layer, the first strip patterns and the semiconductor substrate using the conformal layer and the spacers as a mask.
In accordance with some embodiments of the present disclosure, it can be further understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
For ease of illustration,
A semiconductor substrate 102 is provided, as shown in
A first hard mask layer 104 is formed over the semiconductor substrate 102, as shown in
A first patterned mask layer 106 is formed over the first hard mask layer 104, as shown in
A second hard mask layer 108, a third hard mask layer 110, a fourth hard mask layer 112, a fifth hard mask layer 114 and a sixth hard mask layer 116 are sequentially formed over the first hard mask layer 106, as shown in
A second patterned mask layer 118 is formed over the sixth hard mask layer 116, as shown in
The patterns 202A have body portions 204 and extending portions 206A which protrude from opposite sides of the body portions 204 with respect to the first direction A. The body portions 204 have a dimension D1 in the first direction A and a dimension D2 in the second direction B. The dimension D1 is smaller than the dimension D2. The extending portions 206A have a dimension D3 in the second direction B. The dimension D3 is smaller than the dimensions D1 and D2. The dimension D3 of the extending portions 206A is smaller than the optical proximity correction (OPC) limit of the lithography process. For example, in some embodiments in which a 193 nm ArF lithography process is used, the dimension D3 of the extending portions 206A is smaller than 20 nm.
After the photomask 200 or the photomask 300 is used to expose the photoresist material, the photoresist material may be developed to remove the exposed or unexposed part of the photoresist material, depending on whether a positive photoresist material or a negative photoresist material is used in the lithography process. The patterns 202A (or 202B) are transferred into the photoresist material to form the openings O1. In some other embodiments, the second patterned mask layer 118 may be made of a hard mask layer. For example, a hard mask layer may be formed using a deposition process. A patterned photoresist layer may be formed on the hard mask layer using a lithography process, and then the hard mask layer is etched using the patterned photoresist layer to form second patterned mask layer 118 with the openings O1.
Referring back to
The openings O1 have a dimension D4 in the first direction A and a dimension D5 in the second direction B. Since the patterns 202A (or 202B) of the photomask used in the lithography process have the extending portions 206A (or 206B), the openings O1 are formed with the larger dimension D4 than the dimension D5. The openings O1 have oval-like outlines or eye-like outlines. The ratio of the dimension D4 to the dimension D5 may be in a range from about 1.1 to about 1.5. In addition, the distance between the openings O1 in the first direction A is smaller than the distance between the openings O1 in the second direction B.
A trimming process is performed on the second patterned mask layer 118 to enlarge the openings O1 in the first direction A and the second direction B, as shown in
A spacer layer 130 is formed along the sidewalls and upper surface of the second patterned mask layer 118, and along the upper surface of the sixth hard mask layer 116, as shown in
In some embodiments, the spacer layer 130 is made of dielectric material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). The spacer layer 130 is formed using an atomic deposition process (ALD) process, a chemical vapor deposition (CVD) process, or another suitable technique.
An etching process is performed on the spacer layer 130 to remove the first horizontal portions 130H1 and the second horizontal portions 130H2 of the spacer layer 130. After the etching process, the vertical portions 130V of the spacer layer 130 remain, and are formed into a plurality of spacers 132. The spacers 132 are spaced apart from each other and extend in the first direction A. An etching process is then performed to remove the second patterned mask layer 118, thereby forming a plurality of trenches T3. The trenches T3 are spaced apart from each other and extend in the first direction A, as shown in
A conformal layer 134 is formed along the sidewalls and upper surfaces of the spacers 132, and along the upper surface of the sixth hard mask layer 116, as shown in
The vertical portions 134V of the conformal layer 134 partially fill the openings O2 and the trenches T3. The shrink openings O2 are denoted as openings O3. The vertical portions 134V of the conformal layer 134 merge with each other at the narrower part of the trenches T3, so that one trench T3 is cut by the vertical portions 134V of the conformal layer 134 into several openings O4 in a row. The openings O3 and the openings O4 overlap the strip patterns of the first patterned mask layer 106. The openings O3 may be referred to as core patterns, and the openings O4 may be referred to as gap patterns. The conformal layer 134 and the spacers 132 together serve as a third patterned mask layer 136. The patterned mask layer 136 having the core patterns and the gap patterns is configured as a mask for subsequent etching processes.
In some embodiments, the conformal layer 134 is made of dielectric material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). The conformal layer 134 is formed using ALD process, a CVD process, or another suitable technique.
In some embodiments, the openings O3 are arranged in an array in the first direction A and the second direction B, and the openings O4 are arranged in an array in the first direction A and the second direction B. The openings O3 and the openings O4 are alternately arranged in the second direction B and staggered from each other.
The openings O3 have a pitch Px_O3 in the first direction A and a pitch Py_O3 in the second direction B. The pitch Py_O3 is longer than the pitch Px_O3. The openings O4 have a pitch Px_O4 in the first direction A and a pitch Py_O4 in the second direction B. The pitch Py_O4 may be longer than the pitch Px_O4. The pitch Px_O3 is substantially equal to the pitch Px_O4, and the pitch Py_O3 is substantially equal to the pitch Py_O4. The ratio of pitch Px_O3 to Py_O3 (or pitch Px_O4 to Py_O4) may be in a range from about 0.75 to about
The openings O3 have a dimension D6 in the first direction A and a dimension D7 in the second direction B. The dimension D6 of the openings O3 is longer than the dimension D7 of the openings O3. The openings O3 formed from the openings O1 also have oval-like outlines or eye-like outlines. The ratio of the dimension D6 to the dimension D7 may be in a range from about 1.1 to about 1.5. The openings O4 have a dimension D8 in the first direction A and a dimension D9 in the second direction B. The dimension D8 of the openings O4 is longer than the dimension D9 of the openings O4. The openings O4 are formed from the gaps between the four openings O3, thus having rhombus-like outlines. The ratio of the dimension D8 to the dimension D9 may be in a range from about 1.1 to about 1.5. The dimension D6 of the openings O3 is substantially equal to the dimension D8 of the openings O4, and the dimension D7 of the openings O3 is substantially equal to the dimension D9 of the openings O4.
According to the embodiments of the present disclosure, the openings O1 (
One or more etching processes are performed on the semiconductor structure using the third patterned mask layer 136 to remove respective portions of the sixth mask layer 116, the fifth mask layer 114, the fourth hard mask layer 112, the third hard mask layer 110, the second hard mask layer 108 and the first patterned mask layer 106 exposed from the openings O3 and O4 until the first hard mask layer 104 is exposed, as shown in
Since the openings O4 have substantially the same dimensions as the openings O3 in the first direction A and the second direction B, portions of the first patterned mask layer 106 at locations corresponding to the openings O4 can be completely cut off, and the openings O5 of the first patterned mask layer 106 have uniform sizes. If the openings O4 described above in
One or more etching processes are performed on the semiconductor structure using the island patterns 106A to remove respective portions of the first hard mask layer 104 and the semiconductor substrate 102 exposed from the trenches T1 and the openings O5, as shown in
According to the embodiments of the present disclosure, since the openings O5 of the first patterned mask layer 104 have consistent sizes, the trenches 144, corresponding to the openings O5, also has consistent sizes, which helps to make the transistors formed in or on the active regions 140 have uniform performance (e.g., threshold voltage). In addition, the short circuit problem caused by the connection of adjacent active regions 140 may be also reduced, thereby improving the manufacturing yield of the resulted semiconductor memory device.
Additional components may be formed over the semiconductor structure of FIGS. 9A and 9B to produce a semiconductor memory device. For example, buried word lines are formed extending through the active regions 140; bit lines are formed over the active regions; capacitor structures are formed over the bit lines; and/or other suitable components may be formed over the semiconductor structure. In some embodiments, the semiconductor memory device is a DRAM.
As described above, the embodiments of the present disclosure provide the method for forming the semiconductor structure, which is direct to a self-aligned double patterning (SADP) technology. By adjusting the patterns of the photomask used in the lithography process for forming the core layer (i.e., the second patterned mask layer 118) to have the extending portions 206A or 206B, the core patterns (i.e., the openings O1) of the core layer have a larger pitch in the second direction B and a larger size in the first direction A. As a result, the gap patterns (i.e., the opening O4) and the core patterns (i.e., the openings O3) of the spacer layer (i.e., the third patterned mask layer 136) can be formed to have substantially the same size. Therefore, the trenches 144, formed from the gap patterns and the core patterns, can completely cut off the active regions 140, and the trenches 144 have uniform sizes. Therefore, the uniformity of the performance of the resulting semiconductor memory device may improve, and the manufacturing yield of the semiconductor memory device may be enhanced.
Number | Date | Country | Kind |
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111120048 | May 2022 | TW | national |