METHOD FOR FORMING ULTRA-SHALLOW HIGH QUALITY JUNCTIONS BY A COMBINATION OF SOLID PHASE EPITAXY AND LASER ANNEALING

Abstract

By using a combination of solid phase epitaxy re-growth and laser annealing, the present invention provides a low thermal budget method which allows the crystal lattice of a semiconductor surface to recover after the doping by ion implantation. The low thermal budget limits the out-diffusion of the dopants ions, thus avoiding the enlargement of the doped source/drain regions. Therefore, the method is suited, for instance, for the fabrication of ultra-shallow source/drain regions in MOS transistors elements. The method according to the present invention comprises a first pre-amorphization process in order to limit channeling effects, a doping process by ion implantation and a re-crystallization by solid phase epitaxy, followed by laser annealing.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIGS. 1 a-1c schematically show the fabrication of a junction in a crystalline semiconductor substrate comprising a doping process by ion implantation followed by rapid thermal annealing (RTA) according to prior art techniques;

FIGS. 2 a-2d schematically show the fabrication of a junction in a crystalline semiconductor substrate, which includes a pre-amorphization, a doping process by ion implantation and a re-growth process by solid phase epitaxy (SPE) followed by laser annealing, according to an illustrative embodiment of the present invention;

FIG. 3 schematically shows the fabrication process of a multi-layer structure comprising doped layers with different electrical properties according to an illustrative embodiment of the present invention including a pre-amorphization step and a re-growth process by solid phase epitaxy and the activation of the doping material by laser Annealing; and

FIGS. 4 a-4e schematically show the fabrication process of ultra-shallow junctions for the source/drain regions in a MOS transistor element including a pre-amorphization, doping by ion implantation, re-growth of the implanted regions by solid phase epitaxy and activation of the doping material by laser annealing according to illustrative embodiments.

Claims

1. A method for forming a semiconductor junction, comprising: forming a substantially amorphous layer above a substantially crystalline semiconductor layer formed above a substrate;forming a doped layer in at least one of said substantially amorphous layer and said substantially crystalline semiconductor layer;re-growing said substantially amorphous layer; andactivating dopants in said doped layer by a pulsed radiation anneal process.

2. The method of claim 1, wherein said pulsed radiation annealing process comprises using laser radiation.

3. The method of claim 1, wherein re-growing said substantially amorphous layer comprises heating said substrate without liquefying portions of said substrate.

4. The method of claim 1, wherein re-growing said substantially amorphous layer comprises thermal treating said substrate at a temperature ranging from approximately 600-800° C.

5. The method of claim 1, wherein said substantially amorphous layer is partially formed by performing an ion implantation process.

6. The method of claim 1, wherein said substantially crystalline semiconductor layer is a silicon layer.

7. The method of claim 1, wherein said doped layer is formed by performing an ion implantation process.

8. The method of claim 7, wherein said ion implantation process is performed at an energy of approximately 1 keV or less.

9. The method of claim 1, wherein said pulsed radiation anneal process comprises generating one or more radiation pulses with a duration in the range of approximately one nanosecond to several microseconds.

10. The method of claim 1, wherein said doped layer is formed so as to function as a shallow PN junction of a transistor device.

11. The method of claim 1, wherein said pulsed radiation anneal process is performed after re-growing said substantially amorphous layer.

12. The method of claim 1, wherein said pulsed radiation anneal process is performed prior to re-growing said substantially amorphous layer.

13. The method of claim 1, wherein said steps of forming a doped layer, re-growing said substantially amorphous layer and activating the dopant are repeated more than once during the whole process.

14. A method, comprising: forming at least a portion of source/drain regions in a semiconductor layer formed above a substrate;re-crystallizing said source/drain regions by thermal treating said substrate; andactivating dopants in said portions of source/drain regions by laser annealing said source/drain regions.

15. The method of claim 14, further comprising forming a substantially amorphous region in said semiconductor layer prior to forming said source/drain regions.

16. The method of claim 14, wherein re-crystallizing said source/drain regions comprises performing a solid phase epitaxy process.

17. The method of claim 15, wherein said substantially amorphous region is formed by ion implantation.

18. The method of claim 14, wherein said portion of said source/drain regions are the source/drain extension regions.

19. The method of claim 17, wherein said ion implantation is performed at an energy of approximately 1 keV or less.

20. The method of claim 14, wherein said re-crystallizing is performed at a temperature ranging from approximately 600-800° C.

21. The method of claim 16, wherein said solid phase epitaxy process is performed prior to said laser annealing.

22. The method of claim 16, wherein said solid phase epitaxy process is performed after said laser annealing.