1. Field of the Invention
The present invention generally relates to an alignment method for semiconductors. More particularly, the present invention relates to a method for improving alignment accuracy of the semiconductor fabrication processes.
2. Description of Related Art
As well known in the art, photolithography is critical for the successful fabrication processes of semiconductor devices. Normally, depending on the complexity of the devices, it takes about 10 to 18 photolithographic and exposure processes to complete the fabrication processes of the devices. In order to correctly and accurately transfer the pattern to the chips during the semiconductor fabrication processes, the alignment between the chip and photomask has to be calculated carefully before each exposure, otherwise the chip will be wasted.
In the conventional exposure process, the alignment marks corresponding to the photomask are formed on the chips with desired semiconductor devices, in order to form a scattering site or a diffraction edge. The alignment marks are comprised of zero marks and floating non-zero marks, or metal alignment marker formed of metals and highly reflective to the light. As the alignment light beam irradiates onto the chip, the diffraction pattern resulted from the alignment mark will be reflected to the alignment sensor, or the First Order Diffraction Interferometer Alignment System, so as to achieve the alignment.
Through the photolithographic process, a hard mask layer is commonly formed as a mask for the following etching process to prevent damage toward the regions that is not planned to be etched during the etching process. However, as the hard mask layer is too thick, most of the alignment light beam will be absorbed by the hard mask layer and the alignment accuracy is reduced. Sometimes, if the alignment light bean is completely absorbed and unable to pass the hard mask layer, the alignment failure will happen. On the other hand, if the thickness of the hard mask layer is not enough, it possesses no protective effects and the unexpected regions may be damaged during the etching process, thus reducing the reliability for the devices.
Accordingly, the present invention is directed to provide a method of improving the alignment accuracy for the semiconductor fabrication processes by controlling the thickness of the hard mask layer, so that the light beam can effectively pass through the hard mask layer to improve the alignment precision.
In accordance with one aspect of the present invention, an alignment method for the semiconductor fabrication is provided, by means of controlling the thickness of the hard mask layer. Therefore the regions that are not planned to be etched will not be damaged during the etching process and the reliability of the devices can be improved.
In accordance with another aspect of the present invention, a method for forming an opening is provided, which provides openings with excellent alignment accuracy.
In accordance with yet another aspect of the present invention, a method for improving the precision for the alignment is provided, applied for the photolithographic process aiming at the dielectric layer covered with the hard mask layer. The alignment marks are disposed under the dielectric layer and the hard mask layer has an absorption index and a thickness. The product of the absorption index and the thickness is around 100˜750. Furthermore, the etching ration of the dielectric layer to the hard mask is bigger than 5.
According to a preferred embodiment of the present invention, the material for the hard mask layer can be, for example, titanium nitride (TiN) or tantalum nitride (TaN).
According to a preferred embodiment of the present invention, titanium nitride (TiN) is used as the material of the hard mask layer, and the range for the thickness, for example, can be around 325 Ř475 Å.
According to a preferred embodiment of the present invention, tantalum nitride (TaN) is used as the material of the hard mask layer, and the range for the thickness, for example, can be around 175 Ř275 Å.
According to a preferred embodiment of the present invention, the material for the alignment marker can be, for example, copper (Cu).
In accordance with again another aspect of the present invention, an alignment method for the semiconductor fabrication processes is provided and the processes involved in forming a plurality of alignment markers and a plurality of conductive lines, forming a dielectric layer to cover the alignment markers and conductive lines, and forming a hard mask layer formed over the dielectric layer. The hard mask layer has an absorption constant and a thickness, which the product for the absorption constant and thickness is around 100˜750. Furthermore, the etching ration of the dielectric layer to the hard mask is bigger than 5. Then, a photoresist layer is formed over the hard mask layer. Thereafter, the aligned light beam is used for detection of the alignment marker, which enable the pattern of the photomask to be accurately transferred to the photoresist layer.
According to another preferred embodiment of the present invention directed to the method for the alignment process in fabricating semiconductor, the steps for forming the alignment markers and the conductive lines are comprised of forming a plurality of trenches inside the substrate and filling a metal layer inside the trenches.
According to another preferred embodiment of the present invention, the materials for the alignment markers and the conductive lines are comprised of, for example, copper (Cu).
According to another preferred embodiment of the present invention, the steps for forming the alignment markers and the conductive lines are comprised of forming a metal layer over the substrate, them defining the metal layer to form the alignment marker and conductive lines.
According to another preferred embodiment of the present invention, the materials for the alignment markers and the conductive lines are comprised of, for example, aluminum (Al).
According to another preferred embodiment of the present invention, the materials for the dielectric layer are comprised of, for example, silicon dioxide.
In accordance with another aspect of the present invention, a method for forming an opening applicable for the fabrication of interconnects is provided. The steps are comprised of forming a plurality of alignment markers and a plurality of conductive lines over the substrate, and forming a dielectric layer over the substrate and covering the alignment markers and conductive lines. Then a hard mask layer is formed over the dielectric layer, where the hard mask layer has an absorption constant and a thickness, and the product for the absorption constant and thickness is around 100˜750. Furthermore, the etching ration of the dielectric layer to the hard mask is bigger than 5. Then, a photoresist layer is formed over the hard mask layer. Through the alignment markers, the pattern is transferred to the photoresist layer. Thereafter, the patterned photoresist layer is treated as a mask to remove a portion of the hard mask layer. Then, the hard mask layer is used as the mask to remove a portion of the dielectric layer till exposing those conductive lines.
Though controlling the thickness of the hard mask layer, the present invention affords high alignment precision by allowing the light beam effectively passing through the hard mask layer and the light beam being reflected by the alignment marker to the detector. On the other hand, the alignment method of the present invention will not lose protective (anti-etching) effects even when the hard mask layer is not thick. Besides, the method of this invention can be integrated to the current semiconductor fabrication processes without additional equipments required. Moreover, by using the method for forming openings described in this invention, the pattern and position of the openings formed are with high precision, thus improving the reliability of the semiconductor devices.
It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
In general, during the photolithographic process, a dielectric layer is formed over the alignment markers and a hard mask layer is further formed over the dielectric layer. The material for the alignment markers can be, for example, a metal, and the material for the hard mask layer can be, for example, Titanium nitride (TiN) or Tantalum nitride (TaN). Furthermore, the etching ration of the dielectric layer to hard mask is bigger than 5. Then, the alignment light beam onto the alignment markers generates a diffraction pattern through the alignment markers and the diffraction pattern being reflected to the alignment detector or the first order diffraction interferometer alignment system is used to achieve the alignment. It is noted that the thickness of the hard mask layer will affect the precision (or accuracy) of the alignment during the alignment process.
The equation for the thickness of the hard mask layer according to the present invention is as follows:
Exp (−2×thickness×absorption constant)>attenuated intensity.
The absorption index=4πk/λ
Where “Exp.” is representing the natural log; “thickness” is the thickness of the hard mask layer by using Å as the unit; “absorption constant” is the absorption coefficient of the hard mask layer with the “1/Å” as the unit, and the absorption constant will change according to the materials of the hard mask layer; k is the absorption index, λ is the wave length. The “attenuated intensity” is the attenuated intensity of the alignment light beam.
According to the preferred embodiments of the present invention, the attenuated intensity can be, for example, 5%, therefore, the product of absorption index and thickness preferably ranges between 100˜750 (as shown in the following equation).
100<thickness×absorption index<750
Regarding the equation 1 in
The range of the product of the thickness and the absorption index according to the above embodiments of the present invention is not to limited to these two materials, Tantalum nitride (TaN) and Titanium nitride (TiN). As long as the material is appropriate for the hard mask layer, it is applicable for the range of the product of the thickness and the absorption index.
Therefore, by applying the absorption index of the chosen material into the equation for the range of the product of thickness and absorption index, the preferred thickness range for the hard mask layer can be obtained, in order to improve the alignment precision without losing the anti-etching effect due to the insufficient thickness.
The following paragraphs relate to another embodiment of the present invention, to illustrate the application for the method for improving the alignment precision.
Next, continuing
Then, turning to
Referring next to
Referring now to
According to yet another preferred embodiment of the present invention, the above mentioned formation steps for the opening 214 can be performed after removing a portion of hard mask layer 208 by using the patterned photoresist layer 210 as a mask. The photoresist layer 210 is removed first, and then a portion of dielectric layer 206 is removed to expose conductive line 204 by using the hard mask layer 208 as a mask.
The above mentioned embodiment applies the alignment markers 202 and the alignment light beam for the alignment, therefore, the openings 214 can be positioned accurately and the reliability of the semiconductor devices can be improved. on the other hand, the fabrication process of the present invention can be integrated with the current processes, so that no additional cost will be added.
Thereafter, with reference to
Continuing to
Then, continuing to
Referring to now to
According to yet again another preferred embodiment of the present invention, the above mentioned formation steps for the opening 314 can be done after removing a portion of hard mask layer 308 by using the photoresist layer 310 with pattern 312 as a mask. The photoresist layer 310 is removed, and then a portion of dielectric layer 306 is removed to expose conductive line 304 by using the hard mask layer 308 as a mask.
The above mentioned embodiment applies the alignment markers 302 and the alignment light beam for the alignment, therefore, the opening 314 can be positioned accurately and the reliability of the semiconductors devices can be improved. on the other hand, the fabrication processes of the present invention can be integrated with the currently applied processes, so that no additional equipment is required and no further cost will be added.
Although the above mentioned embodiments apply the alignment method to the fabrication of openings for the metal interconnects, it is not intended to limit the present invention to the precise forms disclosed. Thereby enabling others skilled in the art to utilize the invention in its various embodiments and modifications according to the particular purpose contemplated. The scope of the invention is intended to be defined by the claims appended hereto and their equivalents.
In conclusion of the above description, the present invention provides at least the following advantages:
1. According to the present invention, various materials can be applied to be the hard mask layer with suitable thickness range to improve the alignment precision and remain the anti-etching function.
2. According to the present invention, the alignment method provided herein can be integrated with the current fabrication processes. Therefore, no additional equipment should be purchased and the alignment precision can be improved.
3. According to the formation method of the openings of present invention, the pattern and positions of the openings are with high precision, which improves the reliability of the semiconductor devices.
The embodiments chosen and described are in order to explain the principles and the application of the invention, thereby enabling others skilled in the art to utilize the invention in its various embodiments and modifications according to the particular purpose contemplated. The scope of the invention is intended to be defined by the claims appended hereto and their equivalents.