Patent Application
20070269908
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
In general, aspects of the invention provide methods for planarizing a substrate surface with reduced or minimal defects in surface topography. The invention will be described below in reference to a planarizing process for the removal of dielectric material from a substrate surface by chemical mechanical polishing (CMP) technique.
The CMP processes described herein may be performed by chemical mechanical polishing processing equipment containing two or three platens, such as the Reflexion™ polishing system, the Mirra™ polishing system, and the Mirra™ Mesa™ polishing system, all of which are available from Applied Materials, Inc., of Santa Clara, Calif. Hereinafter, a hybrid CMP system broadly refers to a CMP tool comprising the use of two different type of polish pads such as a high selectivity slurry (HSS) pad and a fixed-abrasive (FA) pad that are mounted on respective platens.
The present invention methods are provided for polishing a substrate containing at least two dielectric layers, such as silicon oxide and silicon nitride with at least one polishing step using a FA pad. The present invention method may be used to remove all, substantially all or a portion of the one or more dielectric layers. For example, a polishing step using a FA pad may be used to remove the topography, and/or residual dielectric material of a dielectric layer.
Topography is broadly defined herein as any projections or recessions formed at the exposed surface of a dielectric material, which provides a non-planar surface. For example, high-density plasma (HDP) chemical vapor deposition of silicon oxide may produce an exposed surface containing peaks of material extending above the bulk silicon oxide material.
Bulk dielectric material is broadly described herein as dielectric material deposited on the substrate in an amount more than sufficient to substantially fill features formed on the substrate surface. The bulk dielectric material may also be referred to as overfill material or blanket material.
Residual dielectric material is broadly defined as any bulk dielectric material remaining after one or more polishing process steps as well as the residue of any additional materials from layers disposed below the bulk dielectric material. Residual material may partially or completely cover the surface a substrate.
Substrates that may be polished by the process described herein may include shallow trench isolation structures formed in a series of dielectric layers, such as silicon oxide disposed over a silicon nitride pad layer.
The invention contemplates polishing dielectric materials conventionally employed in the manufacture of semiconductor devices, for example, silicon dioxide, silicon nitride, and silicon oxynitride.
The invention also contemplates the polishing of other dielectric materials, such as polysilicon, carbon doped silicon carbide, phosphorus-doped silicon glass (PSG), boron-phosphorus-doped silicon glass (BPSG), and silicon dioxide derived from tetraethyl orthosilicate (TEOS), high density plasma chemical vapor deposition (HDP-CVD) silicon oxides (HDP oxides), silane by plasma enhanced chemical vapor deposition (PECVD) can be employed, and combinations thereof.
In one embodiment of a polishing process, a substrate having a first dielectric material, such as silicon oxide, disposed on a second dielectric material, such as silicon nitride, may be first polished with a first polishing composition and an abrasive-free polishing pad to substantially remove the bulk of the first dielectric material, and then be polished with a second polishing composition and a FA pad to remove the remaining first dielectric material disposed on the substrate surface.
An example of an abrasive-free polishing pad is the IC-1000 polishing article commercially available from Rodel Inc., of Phoenix Ariz. The FA pad may include a hard resin fixed-abrasive web, for example, SWR-159 or SWR-521, commercially available from 3M of Minneapolis, Minn. One example of a polishing composition for use with FA pads is a proline or I-proline available from Applied Materials, Inc.
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The deposited dielectric fill material 130 generally has an excess material deposition 145 of bulk dielectric material, that has an uneven surface topography 140 with peak and recesses typically formed over feature definitions 135 having varying widths.
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As previously mentioned, it is critical to control the incoming oxide thickness t before the wafer is transferred to the second platen or the FA pad. The incoming oxide thickness control is particularly important for 300 mm FA web polish because so-called fast-band problem occurs resulting in narrow polish time window of the FA pad. Long polish time will lead to silicon nitride loss in fast-band areas, while short polish time will lead to residual oxide on non-fast band areas.
According to this invention, t is preferably between 200 and 250 angstroms.
The high-selectivity slurry compositions generally have a selectivity of silicon oxide to silicon nitride of greater than about 5:1, and preferably have a selectivity of about 30:1 or greater. The high selectivity compositions may include compositions having abrasive solutions, additives, and solvent. The abrasive solutions, additives, and solvent may be a ratio of X:Y:Z, with X=1 to 20, Y=0 to 20, and Z=0 to 20.
The abrasive solutions may contain between about 10 weight percent (wt. %) and about 30 wt. % of silica abrasive particles or between about 0.5 weight percent (wt. %) and about 5 wt. % of ceria abrasive particles. An example of an abrasive particle is ceria with a particle size of about 300 nm or less in size.
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Step 10: start;
Step 12: sequentially polish the foregoing 3-8 pattern wafers only on the first platen using HSS pad, each of which is polished for different polish time, for example, 70 seconds, 80 seconds and 90 seconds for the first, second and third pattern wafers, respectively, and so on;
Step 14: in-line measure and calculate the removal amount of each of the polished 3-8 pattern wafers and output a substantially linear plot or fitting curve of removal amount vs. polish time thereof (the removal amount is the original thickness of oxide before polishing subtracts the measured thickness of the remaining oxide);
Step 16: sequentially polish the rest of the pattern wafers of the same lot as the foregoing 3-8 pattern wafers on the first platen using the HSS pad, based on the fitting curve of removal amount vs. polish time established by the foregoing 3-8 pattern wafers;
Step 18: sequentially polish the rest of the pattern wafers of the same lot on a second platen using a fixed-abrasive pad to remove the remaining oxide layer and expose the underlying silicon nitride pad layer;
Step 20: (optional): sequentially buff or over-polish the rest of the pattern wafers on a third platen to remove any residual oxide;
Step 22: measure the rest of the pattern wafers;
Step 24: rework the foregoing 3-8 pattern wafers on the second platen using the FA pad;
Step 26: measure the foregoing 3-8 pattern wafers; and
Step 28: end.
An exemplary linear fitting curve of removal amount vs. polish time that is established according to the foregoing 3-8 pattern wafers polished by the first platen is shown in
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Step 30: start;
Step 32: sequentially polish the foregoing 3-8 pattern wafers only on the first platen using HSS pad, which are polished for different polish time;
Step 34: measure and calculate the removal amount of each of the polished 3-8 pattern wafers and output a first fitting curve of removal amount vs. polish time thereof;
Step 36: sequentially polish the foregoing 3-8 pattern wafers on the second platen using FA pad, which are polished for different polish time;
Step 38: in-line measure and calculate the removal amount of each of the polished 3-8 pattern wafers and output a second fitting curve of removal amount vs. polish time thereof;
Step 40: sequentially polishing the rest of the pattern wafers of the same lot on the first platen based on the first fitting curve established by the foregoing 3-8 pattern wafers;
Step 42: sequentially polishing the rest of the pattern wafers of the same lot on a second platen to remove the remaining oxide layer based on the second fitting curve;
Step 44: (optional): sequentially buff or over-polish the rest of the pattern wafers on a third platen to remove any residual oxide;
Step 46: measure the rest of the pattern wafers;
Step 48: rework the foregoing 3-8 pattern wafers on the second platen using the FA pad;
Step 50: measure the foregoing 3-8 pattern wafers; and
Step 52: end.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
