Claims
- 1. A method for in-line monitoring of a via/contact etching process comprising:
forming on a wafer to being processed, a test structure including via/contact holes of different sizes and densities in a layout such that for a particular process, the microloading or RIE lag induced non-uniform etch rate produces under-etch in some regions of the test structure and over-etch in other regions of the test structure; using a scanning electron microscope to produce voltage contrast images; and using the images to distinguish etching differences in the processed wafer.
- 2. A method for in-line monitoring of a via/contact etching process as recited in claim 1 wherein said test structure includes a regular array of discrete regions having via/contact holes provided therein with the holes in the several regions varying in size and/or density across the array.
- 3. A method for in-line monitoring of a via/contact etching process as recited in claim 2 wherein each wafer in a process lot includes said test structure, and wherein the voltage contrast images of each test structure form fingerprint images characterizing the etching process in terms of thickness over-etch or under-etch.
- 4. A method for in-line monitoring of a via/contact etching process as recited in claim 2 wherein each wafer in a process lot includes said test structure, and wherein voltage contrast images of each test structure form fingerprint images used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations.
- 5. A method for in-line monitoring of a via/contact etching process as recited in claim 2 wherein each wafer in a process lot includes said test structure and voltage contrast images of each test structure form fingerprint images used for validating process uniformity.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to U.S. Provisional Application entitled “A Method For InLine Monitoring Of Via/Contact Etching Process Uniformity In Semiconductor Wafer Manufacturing”, Application No. 60/329,917, filed Oct. 16, 2001. The prior application is hereby incorporated hereinto by reference. This application is also related to U.S. Provisional Application entitled “A Method For In-Line Monitoring Of Via/Contact Etching Process Uniformity In Semiconductor Wafer Manufacturing”, Application No. 60/332,016, filed Nov. 21, 2001.
Provisional Applications (1)
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Number |
Date |
Country |
|
60332016 |
Nov 2001 |
US |