Patent Application
20070057202
The performance and yield of semiconductor devices depends on processing methods that enable the confinement of current, carriers, and photons. The performance and yield of these devices also depends on guiding radiation along specific directions within the device. Fabrication using buried heterostructure geometry combines all of these features effectively, and is thus commonly used when manufacturing high power lasers, electro-absorption modulators, and waveguides. For these devices, a mesa is defined in the structure of the device by etching once the basic active region structure is in place. The width of the mesa influences the mode, shape, and laser threshold of the laser, and is involved in determining whether the laser has a single mode operation.
The process of creating a mesa involves the use of either wet chemical etching techniques or dry chemical etching techniques, such as reactive ion etching (RIE) or inductance coupled plasma (ICP) etching. Some wet etching solutions result in the width of the mesa stripes at the center region becoming wider than the edge region and, likewise, the height at the center area may become different than the height at the edge area, typically shallower. On the other hand, if the stripe width is controlled for single mode operation at the edge of the wafer, the stripe width will be too wide at the center of the mesa, creating undesirable higher order modes during operation of the device. In contrast, dry etching can result in very uniform stripe width. However, a drawback to dry etching is that the surface of the wafer can be very rough after the etching process. Hence, whatever etching method is chosen, optimal device performance and device yield cannot be achieved.
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, an etching stop layer grown over the substrate, and an active region layer grown on the etching stop layer. The active region layer is further grown or deposited opposite the substrate, and is thus disposed opposite the substrate. The Fe doped InP layer is deposited on both sides of the mesa for current and index confinement.
Furthermore, the invention provides embodiments and other features and advantages in addition to or in lieu of those discussed above. Many of these features and advantages are apparent from the description below with reference to the following drawings.
Embodiments in accordance with the invention provide for a semiconductor device with an etching stop layer. The stop layer allows buried heterostructure semiconductor devices to be built reliably and consistently with a high yield.
Optionally, buffer layer 104 is deposited and disposed on the substrate. In this exemplary embodiment, buffer layer 104 is made from n type InP. Buffer layer 104 minimizes the defect density in substrate 102. Buffer layer 104 is typically about 1.5 μm thick.
Etching stop layer 106 is deposited and disposed on buffer layer 104, or may be deposited directly on substrate 102. Etching stop layer 106 is made of materials resistant to etching processes. Etch-resistant materials suitable for use in etching stop layer 106 include InGaAsP and InGaAs. Etching stop layer 106 in the exemplary embodiment is disposed between active region layer 110 and buffer layer 104 or substrate 102. Etching stop layer 106 in the exemplary embodiment is also very thin, such as about 10 nm. The thickness of etching stop layer 106 may vary between about 5 nm and 20 nm, in order to minimize problems with light propagation in the waveguide. The separation between etching stop layer 106 and active region layer 110 is determined by dielectric stripe width 216, as shown in
Deposited and disposed above etching stop layer 106 is n-cladding layer 108. N-cladding layer 108 in the exemplary embodiment is made from n type InP.
Deposited and disposed above n-cladding layer 108 is active region layer 110. Active region layer 110 may be formed from a plurality of sub-layers, each comprising different materials. In the exemplary embodiment, active region layer 110 forms a laser or waveguide, though active region layer could form any of a number of semiconductor devices. Materials suitable for use in active region layer 110 include InP, InGaAs, InGaAsP, InAlAs, AlInGaAs, and multi-layers made up from these materials.
Deposited and disposed above active region layer 110 is p-cladding layer 112. P-cladding layer 112 is made from a p-type material. A p-type material is the type of conduction material used to form a PN junction. In the exemplary embodiment, p-cladding layer 112 is made from Zn doped InP.
Deposited and disposed above p-cladding layer 112 is surface freshening layer 114. This layer has the dual purpose of defining the mesa etch profile and providing a fresh surface for regrowth of additional layers. In the exemplary embodiment, surface freshening layer 114 is made from InGaAsP, though surface freshening layer 114 may also be made from materials such as InGaAs. Surface freshening layer 114 will be removed just before p-cladding layer 720, shown in
In semiconductor device 100, the various layers are disposed relative to substrate 102. Thus, for example, etching stop layer 106 is disposed over substrate 102. Similarly, active region layer 110 is disposed over etching stop layer 106 and is disposed over substrate 102. For this reason, active region layer 110 may be characterized as disposed over etching stop layer 106 and opposite substrate 102. The other layers, such as layers 104, 106, 108, 110, 112, and 114, may be similarly characterized in terms of location relative to substrate 102. Thus, for example, once p-cladding layer 112 is added, p-cladding layer 112 may be characterized as over active region layer 110 and disposed opposite substrate 102 and etching stop layer 106.
Each of the layers shown in
Dielectric stripe 216 is added to top of surface freshening layer 214. Dielectric stripe 216 is used to define the mesa width. Dielectric stripe 216 in the exemplary embodiment is made from SiNx or SiO2. The thickness of dielectric stripe 216 is about 500 nm, but may vary between about 450 nm and about 550 nm.
In the exemplary embodiment shown,
After formation of mesa 402 using dry etching techniques, semiconductor device 400 is subjected to a selective wet etching solution. A selective wet etching solution only dissolves or attacks certain, targeted materials so that only certain layers are worn. In the exemplary embodiment, a solution of HCL and deionized water (H2O) is used with a ratio of HCL:H20=2:1 or 1:1 in order to smooth the surface on etching stop layer 408. However, other suitable solutions may be used, so long as any remaining portion of n-cladding layer 410 is removed above etching stop layer 408. This wet etching process creates a very smooth surface across the surface of etching stop layer 408. In addition, a portion of n-cladding layer 410 near etching stop layer 408 is also worn, slightly narrowing the base of n-cladding layer 410. Similarly, a portion of p-cladding layer 414 is worn near active region layer 412, slightly narrowing the base of p-cladding layer 414.
After wet etching with a selective solution, semiconductor device 500 is etched using a non-selective etching solution. A non-selective etching solution dissolves or attacks all of the materials of semiconductor device 500. In the exemplary embodiment, a solution of HBr, hydrogen peroxide (H202), and deionized water (H20) is used as the non-selective etching solution. A ratio of HBr:H202:H20=20:4:200 in order to wear a portion of all of the layers, especially from the sides of mesa 502. However, other suitable solutions may be used, so long as damage from dry etching is removed and mesa 502 sidewalls are made smooth.
As a result of the process to this point, the width of mesa 502 is carefully and reproducibly controlled in order to ultimately control the performance of the finished device. In addition, the width of mesa 502 shrinks such that dielectric stripe 518 extends over the edges of mesa 502. Because dielectric stripe 518 extends past the edges of mesa 502, dielectric stripe 518 will prevent over-shoot of a later-added current blocking layer, such as current blocking layer 618 shown in
After etching with a non-selective solution, current blocking layer 618 is deposited or added above buffer layer 606, and around mesa 602. In the exemplary embodiment, current blocking layer 618 is made of Fe doped InP and has a thickness of about 3 μm. Current blocking layer 618 may vary in thickness between about 2.5 μm and about 3.5 μm. Current blocking layer 618 provides current confinement at the active region.
After adding current blocking layer 618, diffusion stopping layer 620 is deposited or added above current blocking layer 618 and around mesa 602. In the exemplary embodiment, diffusion stopping layer 620 is made of Si doped InP having a thickness of about 0.4 μm. Thus, diffusion stopping layer 620 is adapted to block diffusion of Zn.
After adding current blocking layer 716 and diffusion stopping layer 718, the dielectric stripe layer 622 in
While what has been described constitute exemplary embodiments in accordance with the invention, it should be recognized that the invention can be varied in numerous ways without departing from the scope thereof. Because embodiments in accordance with the invention can be varied in numerous ways, it should be understood that the invention should be limited only insofar as is required by the scope of the following claims.
