Patent Application
20250006492
The present disclosure relates to the field of semiconductor materials for microelectronic components. The present disclosure relates, in particular, to a process for fabricating a composite structure comprising a thin layer of single-crystal silicon carbide on a carrier substrate made of polycrystalline silicon carbide.
SiC is increasingly widely used to fabricate innovative power devices, to meet the needs of growing fields of application of electronics, such as electric vehicles, in particular.
Power devices and integrated power-supply systems based on single-crystal silicon carbide are able to manage a much higher power density than their conventional silicon equivalents, and to do so with active regions of smaller size. In order to further limit the dimensions of power devices on SiC, it would be advantageous to fabricate vertical components rather than lateral components. To do this, vertical electrical conduction, between an electrode placed on the front face of the SiC structure and an electrode placed on the back face, must be permitted by the structure.
Nevertheless, high-quality single-crystal SiC (c-SiC) substrates intended for the microelectronics industry remain expensive and difficult to supply in large sizes. It is thus advantageous for layer transfer solutions to be used to produce composite structures typically comprising a thin layer of single-crystal SiC (obtained from the high-quality c-SiC substrate) on a lower cost carrier substrate, for example, made of polycrystalline SiC (p-SiC).
One well-known thin-layer transfer solution is the Smart Cut® process, which uses implantation of light ions in a single-crystal donor substrate, and joining by direct bonding, at a bonding interface, to a carrier substrate. The transfer of the thin layer, derived from the donor substrate, to the carrier substrate is carried out by way of a fracture along a buried weak plane generated by the implantation of light ions.
Another known transfer solution, in particular, for silicon substrates, is the Eltran® process, which involves a porous layer on which the thin single-crystal layer is grown epitaxially, and joining by direct bonding to the carrier substrate. The transfer of the thin layer to the carrier substrate is carried out by way of a separation in the porous layer.
The present disclosure relates to an alternative solution to those of the prior art. It relates to a process for fabricating a composite structure comprising a thin layer made of single-crystal SiC positioned on a carrier substrate made of polycrystalline SiC. It also relates to an intermediate structure obtained during the fabrication process.
The present disclosure relates to a process for fabricating a composite structure comprising a thin layer made of single-crystal silicon carbide positioned on a carrier substrate made of polycrystalline silicon carbide, the process comprising:
According to other advantageous and non-limiting features of the present disclosure, taken individually or in any technically feasible combination:
The present disclosure also relates to an intermediate structure comprising:
Other features and advantages of the present disclosure will become apparent on reading the following detailed description of example embodiments of the present disclosure, with reference to the appended figures, in which:
The figures are schematic representations that, for the sake of readability, have not been drawn to scale. In particular, the thicknesses of the layers along the z-axis are not to scale with respect to the lateral dimensions along the x- and y-axes. The relative thicknesses of the layers with respect to one another have not necessarily been respected in the figures.
The present disclosure relates to a process for fabrication of a composite structure 100 comprising a thin layer 1 made of single-crystal silicon carbide (c-SiC will be used below to refer to single-crystal silicon carbide) positioned on a silicon carbide carrier substrate 20 (
The process first comprises a step a) of providing an initial substrate 10 made of single-crystal silicon carbide (
Step a) also comprises the provision of a carrier substrate 20 made of polycrystalline silicon carbide having a front face 20a and a back face 20b (
The carrier substrate 20 may be produced by a conventional technique such as sintering or chemical vapor deposition. The carrier substrate 20 is preferably in a form identical to that of the initial substrate 10, typically in the form of a wafer having a typical diameter and thickness mentioned above with reference to the initial substrate 10. The surface roughness of the front face 20a of the carrier substrate 20 is advantageously chosen to be less than 1 nm Ra, at least when this face is intended to be directly joined in a subsequent step d) of the process.
The process then comprises a step b) of porosification applied to the initial substrate 10, to form a porous layer 11 (
Advantageously, the porous layer 11 has a thickness of between 0.5 μm and 5 μm. The degree of porosification is preferably between 10% and 70%, and the size of the pores is typically between 1 nm and 50 nm.
These characteristics are favorable, firstly to the crystallization in contact with the porous layer 11 (step e) of the process) of a layer 21 made of amorphous silicon carbide in single-crystal form, which layer is intended to form the thin layer 1 of the composite structure 100; secondly, the characteristics of the porous layer 11 are suitable for allowing and facilitating the separation within this layer, in a step f) of the process, while providing a sufficient mechanical strength during the previous steps.
The next step c) of the fabrication process according to the present disclosure corresponds to the formation of a superficial layer 21, 12 made of amorphous silicon carbide, at least on the front face 20a, 10a of the carrier substrate 20 or of the initial substrate 10.
According to a first embodiment, it is the substrate 20 that is provided at least on the front face 20a thereof with the superficial layer 21 made of amorphous silicon carbide (a-SiC) (
According to a second embodiment, the superficial layer 12 made of amorphous silicon carbide is formed on at least the front face 10a of the initial substrate 10, namely on the porous layer 11 (
According to a third embodiment, a superficial layer 21 is formed on the front face 20a of the carrier substrate 20 and another superficial layer 12 is formed on the porous layer 11, itself positioned on the initial substrate 10.
In one or other of the aforementioned embodiments, the superficial layer 21, 12 could also be formed on the back face 20b, 10b of the substrates 20, 10 in question.
Irrespective of the embodiment, the superficial layer 21, 12 advantageously has a total thickness of less than or equal to 10 μm.
In order to form this superficial layer 21, 12, step c) comprises, according to a first variant, the deposition of an a-SiC layer on the substrate 20, 10 in question. The deposition of amorphous SiC may be carried out by a chemical vapor deposition (CVD) technique, for example, plasma-enhanced CVD (PECVD), or direct liquid injection CVD (DLI-CVD), by a physical vapor deposition technique, or by any other known technique. In the case of CVD deposition, a deposition temperature below 1100° C., or below 1000° C., is preferred. Regarding the deposition precursors (methane or silane chemistry), the C/Si ratio will preferably be chosen to be greater than or equal to 1.
The deposition techniques mentioned make it possible to form a superficial layer 21, 12, the thickness of which may typically vary between 100 nm and 10 μm, for example, around 1 μm. Similarly, the doping of the superficial layer 21, 12 made of a-SiC may be adjusted easily when it is formed by one of these techniques. It may notably be highly doped (usually of n-type, but optionally of p-type): for this, it comprises dopant species in a concentration of greater than 1019/cm3, or of greater than 1020/cm3. It should be remembered that the superficial layer 21, 12 is intended to be crystallized, at least partially, in single-crystal form, in order to form the thin layer 1 of the composite structure 100. Thus, it may be highly doped in order to give rise to a thin layer 1 having a low resistivity, depending on the requirements of the intended application.
According to a second variant, step c) comprises the amorphization of a surface layer of the substrate in question, in order to form the superficial layer 21, 12 made of a-SiC. This amorphization maybe carried out by a known technique, such as ion bombardment (for example, with Si or C ions) or neutron bombardment, with appropriate energies for forming an amorphous superficial layer 21, 12 having the desired thickness.
In the case of an amorphization of a surface layer of the substrate 20 (first embodiment and third embodiment), the polycrystalline structure of the carrier substrate 20 may be rendered amorphous, for example, by ion bombardment.
According to this second variant of formation of the superficial layer 21, 12, the thickness of the superficial layer 21, 12 is preferably less than 1 μm, typically on the order of a hundred to several hundreds of nanometers.
The fabrication process according to the present disclosure next comprises a step d) involving the joining of the initial substrate 10 and the carrier substrate 20 at their respective front faces 10a, 20a (
In the first embodiment (
In the second embodiment (
Lastly, in the third embodiment (
As will be specified below, irrespective of the embodiment, the bonding interface 3, 3′, 3″, in step d), may involve direct contact between the surfaces joined or indirect contact between the surfaces joined, via a bonding layer.
The joining of step d) is based on direct bonding by molecular adhesion. As is well known per se, such bonding does not require an adhesive material, as bonds are made at the atomic level between the joined surfaces. Several types of molecular adhesion bonding exist, which differ, in particular, in terms of their temperature, pressure, atmosphere conditions or treatments prior to bringing the surfaces into contact. Mention may be made of room-temperature bonding with or without prior plasma activation of the surfaces to be joined, atomic diffusion bonding (ADB), surface-activated bonding (SAB), etc.
The joining step d) can comprise, prior to bringing the faces to be joined into contact, conventional sequences of chemical cleaning (for example, RCA cleaning) and of surface activation (for example, by way of oxygen or nitrogen plasma) or other surface preparations (such as scrubbing), which are likely to promote the quality of the bonding interface 3, 3′, 3″ (low defect density, high adhesion energy).
As mentioned previously, step d) may optionally comprise, prior to bringing the faces of the substrates 20, 10 to be joined into contact, the formation of a bonding layer on one and/or the other of the faces. The bonding layer may therefore be deposited (for example, by chemical vapor deposition CVD) on the porous layer 11 and/or on the superficial layer 21 (in the first embodiment), directly on the carrier substrate 20 and/or on the superficial layer 12 (in the second embodiment) or on one and/or the other of the superficial layers 21, 12 (in the third embodiment).
The bonding layer may be composed of at least one material chosen from silicon, nickel, titanium, tungsten, etc. The bonding layer is preferably of reduced thickness. Typically, the total thickness of the bonding layer is less than or equal to 10 nm, or less than or equal to 5 nm. In the first embodiment, the bonding layer may have a small thickness enabling the segmentation thereof in the form of nodules or the dissolution thereof during the heat treatment of the subsequent step e). This then provides a direct contact, at least locally, between the porous layer 11 and the superficial layer 21. this direct contact is essential for the correct implementation of the crystallization taking place in the next step e). If the bonding layer is made of semiconductor material (such as silicon, in particular), it could be doped so as to promote vertical electrical conduction.
As illustrated in
Lastly,
The next step e) of the fabrication process involves a heat treatment applied to the first intermediate structure 30, 30′, 30″, at a temperature above 900° C., in order to crystallize the superficial layer 21, 12 (
The superficial layer 21, 12 crystallizes, via a solid-phase epitaxy phenomenon, in the form of single-crystal silicon carbide, starting from an interface of direct contact between the porous layer 11 (the SiC of which has a single-crystal structure) and the superficial layer 21, 12 made of a-SiC. The superficial layer crystallized in single-crystal form forms the thin layer 1.
It may be that only a portion of the superficial layer 21, 12 crystallizes in single-crystal form. This is because the crystallization may occur at least partly in the form of polycrystalline silicon carbide, starting from the contact interface with the carrier substrate 20. An intermediate layer 22 is then formed, extension of p-SiC of the carrier substrate 20 up to the thin layer 1 made of c-SiC. In other words, the intermediate layer 22 is interposed between the carrier substrate 20 and the thin layer 1. The interface between the intermediate layer 22 and the thin layer 1 has the advantage of being perfectly closed as it is defined from the same a-Si material (superficial layer(s) 21, 12) by the meeting of the c-SiC and p-SiC crystallization fronts. This is an interesting advantage compared to a bonding interface between two materials of different crystalline nature (p-SiC/c-SiC, for example), the complete closure of which is notably dependent on the roughness and surface finish of the materials before joining.
In order to obtain such an intermediate layer 22, provision is notably made, if no superficial layer 21 is present on the carrier substrate 20 (i.e., in the second embodiment), for the superficial layer 12 made of a-Si (on the porous layer 11 side) to be in direct contact with the carrier substrate 20, in the absence of a bonding layer or by the use of a discontinuous bonding layer, for example, a bonding layer that forms a set of nodules between which the carrier substrate 20 is in direct contact with the superficial layer 12.
Step e) leads to a second intermediate structure 40 being obtained, irrespective of the embodiment implemented, in which structure all or part of the superficial layer(s) 21, 12 is crystallized in single-crystal form in order to form the thin layer 1 (
The fabrication process finally comprises a step f) of separation in the porous layer 11 of the second intermediate structure 40, in order to obtain the composite structure 100 on the one hand and the remainder 10′ of the initial substrate on the other hand (
The separation step f) is carried out by applying a mechanical stress to the second intermediate structure 40. The stress may be exerted by the pressing and/or inserting of a tool (for example, a blade or other beveled shape) on the edge of the intermediate structure 40, opposite the porous layer 11. Alternatively, the mechanical stress may be applied by waterjet or air jet, directed toward the edge of the structure 40, still opposite the porous layer 11. Irrespective of the separation technique used, the mechanical stress applied must be suitable for propagating a fracture wave in the porous layer 11, which is of lower mechanical strength compared to the other layers or interfaces in the second intermediate structure 40.
By taking care to protect the free faces of the second intermediate structure 40, the separation could optionally be promoted by lateral chemical etching of the porous layer 11.
At the end of the separation step f), the free face 1a of the thin layer 1 of the composite structure 100 may have residues 11r of porous layer (
The process according to the present disclosure may therefore comprise a step g) of mechanical and/or chemical treatment(s) of the composite structure 100, in order to remove residues 11r of porous layer 11 from the front free face 1a of the thin layer 1 and/or to correct the thickness uniformity of the composite structure 100 (
The step g) may comprise a chemical mechanical polishing (CMP) and/or a chemical or plasma treatment (etching or cleaning) and/or a mechanical treatment (grinding), in order to remove the residue 11r.
The step g) may also comprise cleaning operations of Caro (piranha etch) and/or SC1/SC2 (Standard Clean 1, Standard Clean 2) and/or HF (hydrofluoric acid) type, or an N2, Ar or CF4 plasma, to further improve the quality of the free face 1a of the thin layer 1.
The step g) may comprise a heat treatment, applied to the composite structure 100, at a temperature of between 1000° C. and 1900° C., for around one hour and up to several hours. This heat treatment may be carried out before or after the abovementioned mechanical and/or chemical treatments(s). The objective of the heat treatment is to stabilize the composite structure 100 by noticeably developing, where appropriate, the crystalline quality of the thin layer 1, such that the structure 100 is perfectly compatible with subsequent heat treatments at very high temperatures, which are required for the fabrication of components on and/or in the layer 1.
Lastly, the fabrication process may comprise a step of reconditioning the remainder 10′ of the initial substrate for reuse as initial substrate 10 for a new composite structure 100 (
Of course, the present disclosure is not limited to the embodiments and to the examples that have been described, and variant embodiments can be added to it without departing from the scope of the invention as defined by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| FR2110624 | Oct 2021 | FR | national |
| FR2110626 | Oct 2021 | FR | national |
This application is a national phase entry under 35 U.S.C. § 371 of International Patent Application PCT/FR2022/051774, filed Sep. 21, 2022, designating the United States of America and published as International Patent Publication WO 2023/057700 A1 on Apr. 13, 2023, which claims the benefit under Article 8 of the Patent Cooperation Treaty to French Patent Application Serial No. FR2110624, filed Oct. 7, 2021 and to French Patent Application Serial No. FR2110626, filed Oct. 7, 2021.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/FR2022/051774 | 9/21/2022 | WO |
