The invention relates to a method for the manufacturing of a compound semiconductor field effect transistor having a fin structure, and to a compound semiconductor field effect transistor having a fin structure.
Metal semiconductor field effect transistor (MESFET) devices based on gallium arsenide (GaAs), that is to say a compound semiconductor including the chemical element gallium (Ga) from the third main group of the periodic system and the chemical element arsenic (As) from the fifth main group of the periodic system, are well-known devices having three electrical terminals (three-terminal devices), which devices are used in diverse analog applications and digital applications at microwave frequencies. Compared with conventional silicon technology (Si technology), GaAs material systems have better transport properties (e.g., five times higher electron mobility and higher low field electron velocity) and therefore have a better noise performance at microwave frequencies and millimeter wave frequencies.
In contrast to an Si substrate, a GaAs substrate is semi-insulating and consequently enables a greater device functionality through epitaxial growth of different layers on the same substrate. A GaAs substrate is therefore well suited to integration in optoelectronic devices.
Since GaAs has a larger band gap than silicon, GaAs-based integrated circuits (ICs) can be used at higher temperatures and thus at higher power levels.
In many digital IC designs a principal aim hitherto has been to reduce the power consumption without simultaneously sacrificing the speed performance. Similarly to silicon-based devices, GaAs-based devices, too, have also been aggressively miniaturized or scaled down to the sub-micron range (e.g. 2 μm to 0.1 μm). In the sub-100-nm range, the device performance, to put it another way the performance of a device, is often limited by the so-called short-channel effects, whereby further scaling becomes difficult, if not even impossible. These effects are usually manifested in the form of a reduction in the transconductance, an increase in the output conductance and a shift in the threshold voltage if the gate length is reduced.
Another manifestation of the short-channel effects consists in an increase in the sub-threshold current. Particularly for low-power applications, or for high-speed applications, in which the devices operate near the pinch-off region, precise control of the sub-threshold drain current and of the threshold voltage is necessary.
In order to overcome future technological challenges, therefore, there is a need for new device architectures and/or new material combinations which have a better low-power performance and a better high-speed performance.
Field effect transistor devices having a fin structure (fin field effect transistor, FinFET) have been proposed in this connection.
A FinFET is a structure having two gates (so-called double-gated structure) which contains a channel region or channel formed in a vertical fin. The use of two lateral gates or side gates in FinFETs is advantageous in order to suppress the short-channel effects. A FinFET, with regard to its layout and its production, is comparable with existing planar MOSFETs (metal oxide semiconductor field effect transistor). It likewise enables a selection or bandwidth of channel lengths, CMOS (complementary metal oxide semiconductor) compatibility and a high packing density.
Various FinFET architectures, which are based on silicon (Si) material systems and on silicon-silicon/germanium (Si/SiGe) material systems, and improve the performance of the devices as far as the control of the short-channel effects and the current driver capability are concerned, have been reported to date (see, e.g., US 2005/073005 A1; WO 2005/010944 A2; WO 2004/049406 A1; WO 2004/068585 A1).
Only planar (that is to say that all three device electrodes are situated on one and the same GaAs surface) or quasi-planar (i.e., recess-gate structures) GaAs-based MESFETs have been disclosed hitherto, see, e.g., U.S. Pat. No. 5,536,666; U.S. Pat. No. 5,514,606; EP 0 517 443 A2; U.S. Pat. No. 5,350,702. The previous documents concentrated principally on improving burn-out and/or the breakdown voltage characteristic (U.S. Pat. No. 5,536,666; U.S. Pat. No. 5,514,606), an increased Schottky barrier height (EP 0 517 443 A2) and an improved gain performance through the use of a dual-gate structure, that is to say two gate electrodes situated close together and between the source-drain contacts (U.S. Pat. No. 5,350,702). However, no FinFET structures or MuGFET structures are known in the art for GaAs material systems, or more generally for compound semiconductor material systems.
Other references, such as U.S. Pat. No. 5,432,356; US 2005/0205859 A1; US 2002/0139994 A1 disclose field effect transistor devices having a plurality of layers formed one above another, which layers each contain a III-V semiconductor material.
Aspects of the invention provide a design for a double-gate or multi-gate compound semiconductor field effect transistor having a fin structure.
As an example, a method is disclosed to manufacture a compound semiconductor field effect transistor having a fin structure. A compound semiconductor field effect transistor having a fin structure is also disclosed.
A number of exemplary configurations of the invention are disclosed. The further configurations of the invention that are described in connection with the method for the manufacturing of a compound semiconductor field effect transistor having a fin structure also apply analogously to the compound semiconductor field effect transistor having a fin structure.
A first embodiment of the invention provides a method for the manufacturing of a compound semiconductor field effect transistor having a fin structure. A first layer is formed on or above a substrate. The first layer contains a first compound semiconductor material. A second layer is formed on the first layer. The second layer contains a second compound semiconductor material. A third layer is formed on the second layer. The third layer contains a third compound semiconductor material. A cap layer is formed on at least one partial region of the third layer. The cap layer contains a fourth compound semiconductor material. A fin structure is formed by patterning the second layer, the third layer and the cap layer. A first source/drain region is formed from a first partial region of the cap layer and a second source/drain region is formed from a second partial region of the cap layer. A gate region is formed on at least one partial region of at least one sidewall of the fin structure and/or on a partial region of an upper surface of the third layer.
In another embodiment, the invention provides a compound semiconductor field effect transistor having a fin structure. A first layer is formed on or above a substrate, wherein the first layer contains a first compound semiconductor material. A second layer is formed on the first layer, wherein the second layer comprises a second compound semiconductor material. A third layer is formed on the second layer, wherein the third layer comprises a third compound semiconductor material. A cap layer is formed on at least one partial region of the third layer, wherein the cap layer comprises a fourth compound semiconductor material. The second layer, the third layer and the cap layer are patterned in such a way that a fin structure is formed. A first source/drain region is formed from a first partial region of the cap layer, and a second source/drain region is formed from a second partial region of the cap layer. A gate region is formed on at least one partial region of at least one sidewall of the fin structure and/or on a partial region of an upper surface of the third layer.
One aspect of the invention can be seen in the fact that a field effect transistor having a fin structure, for example, a fin field effect transistor (FinFET) or a multi-gate field effect transistor (MuGFET), based on compound semiconductor materials such as III-V compound semiconductor materials, for example, is realized.
The expressions “fin structure” and “fin” are used alternately and synonymously hereinafter. A fin field effect transistor (FinFET) is understood to mean a field effect transistor having a fin structure or a fin. A multi-gate field effect transistor (MuGFET) is understood to mean a fin field effect transistor (FinFET) in which the channel is driven by a gate structure from more than two sides. A MuGFET in which the channel is driven from three sides is also referred to as a triple-gate field effect transistor or as a tri-gate field effect transistor.
Another aspect of the invention can be seen in the fact that a design for a FinFET having two gates (double-gated FinFET) and a tri-gate FET or a multi-gate FET based on compound semiconductor materials is provided. The invention provides, in particular, a method for the manufacturing of a FinFET or of a multi-gate FET based on high-mobility material systems which have very good (charge carrier) transport properties and can therefore be advantageously used for applications in the microwave frequency range and in the millimeter wave frequency range.
By way of example, a FinFET or MuGFET based on GaAs material is provided. Similarly to a planar MESFET, a GaAs-MuGFET can be regarded as a device having three (electrical) terminals (three-terminal device), which device has a first terminal, the source terminal or source, a second terminal, the drain terminal or drain, and a third terminal, the gate terminal or gate. The majority charge carriers (electrons in this case) can flow from the source region to the drain region and in the process can pass the gated region along a channel. The current through the channel can be controlled by the third terminal, that is to say the gate terminal.
The length of the gate can usually be used to influence or define the speed performance of the device (that is to say of the transistor), and hence how fast, e.g., a circuit can operate.
Another aspect of the invention can be seen in the fact that in the compound semiconductor field effect transistor having a fin structure, more than one gate can be used for more effectively controlling the channel electrons and, consequently, for suppressing the short-channel effects discussed above. The channel for a GaAs-based FinFET or MuGFET can be formed as a thin rectangular island (bridge) composed of GaAs material having a predetermined height, which island or bridge is usually referred to as a “fin”. The gate can envelope the fin in such a way that the channel is controlled from both sides of the vertical partial region of the fin structure, whereby a gate control is provided which is better than in the case of planar MESFETs having only a single gate (single-gate MESFET).
One aspect of the invention can be seen in the fact that the invention provides a layout and a method for the manufacturing of compound-semiconductor-material-based fin field effect transistors (FinFETs) having two lateral gates, and multi-gate field effect transistors (MuGFETs) or tri-gate field effect transistors having three gates (two lateral gates and a third gate on the upper surface of the fin).
Both types of devices, i.e., FinFETs and MuGFETs, can be manufactured in the same process sequence, e.g., using the same mask and without additional process steps. The total effective width of the device is twice the fin height (2×Hfin).
One advantage of the invention can be seen in the fact that the layout and the manufacturing method are similar to those of already existing planar GaAs-MESFETs. By way of example, the devices can be processed with the aid of a combination of conventional optical lithography and electron lithography techniques.
In accordance with one configuration of the invention, the substrate used for the compound semiconductor field effect transistor having a fin structure contains a semi-insulating material.
In accordance with another configuration of the invention, the substrate contains a III-V compound material.
In the case of a substrate containing a III-V compound material, the substrate can contain a gallium arsenide material (GaAs material), e.g., a layer composed of a semi-insulating GaAs material.
In accordance with another configuration of the invention, the substrate contains an indium phosphide material (InP material).
In another configuration of the invention, prior to forming the first layer, a buffer layer is formed on the substrate, and the first layer is formed on the buffer layer.
The buffer layer can be formed using a growth method such as, for example, a molecular beam epitaxy (MBE) growth method or a metal organic chemical vapor deposition (MOCVD) method.
The buffer layer can contain a fifth compound semiconductor material.
The buffer layer can improve the quality of a subsequently formed material layer, e.g., the quality of the first layer, compared with forming the material layer (e.g., the first layer) directly on the substrate.
In accordance with another configuration of the invention, at least one of the following layers contains a III-V compound semiconductor material: the first layer; the second layer; the third layer; the cap layer; the buffer layer.
In accordance with another configuration of the invention, at least one of the following layers contains a GaAs material: the second layer, the third layer, the cap layer, the buffer layer.
By way of example, the buffer layer can contain a non-doped or undoped GaAs material, e.g., in the case of a GaAs substrate. As an alternative, the buffer layer can contain a non-doped (undoped) InP material, e.g., in the case of an InP substrate.
In another configuration of the invention, the buffer layer has a thickness of approximately 500 nm±100 nm.
In accordance with another configuration of the invention, at least one of the following layers is formed using a growth method such as, for example, a molecular beam epitaxy (MBE) growth method or a metal organic chemical vapor deposition (MOCVD) method: the first layer, the second layer, the third layer, the cap layer, the buffer layer.
In accordance with another configuration of the invention, the first layer contains a semiconductor material having a large band gap (wide-band-gap semiconductor material), in other words a semiconductor material having a high energy band gap, e.g., having an energy band gap of between approximately 1.5 eV and 2.2 eV.
Clearly, the first layer, which contains a wide-band-gap material, that is to say a material having a high energy band gap, effectively suppresses the charge carrier transport, in other words the movement of the charge carriers, into the substrate by creating a potential barrier. The first layer is therefore also referred to as a barrier layer or as a separating layer.
The thickness of the first layer (or barrier layer) can be chosen such that the time required for forming the barrier layer (e.g., by means of a growth method) is minimized, while at the same time an effective barrier for charge carrier transport is nevertheless ensured.
In accordance with one configuration of the invention, the first layer contains an AlAs material, e.g., a non-doped (undoped) AlAs material. In this case, the thickness of the first layer can be approximately 20 nm to 60 nm. However, the first layer can also have other dimensions. An undoped AlAs material can have an energy band gap of approximately 2.16 eV.
In another configuration of the invention, the first layer contains an Al0.3Ga0.7As material, e.g. a non-doped (undoped) Al0.3Ga0.7As material, and the thickness of the first layer can be approximately 10 nm to 20 nm in this case. However, the first layer can also have other dimensions. An undoped Al0.3Ga0.7As material can have an energy band gap of approximately 1.785 eV.
In accordance with another configuration of the invention, the first layer contains an Al0.48In0.52As material, e.g., a non-doped (undoped) Al0.48In0.52As material, and the thickness of the first layer can be approximately 100 nm to 500 nm in this case. However, the first layer can also have other dimensions. An undoped Al0.48In0.52As material can have an energy band gap of approximately 1.5 eV.
In accordance with another configuration of the invention, the second layer is formed as a spacer layer, and the third layer formed on the second layer, i.e., the spacer layer, is formed as a channel layer or as a channel of the field effect transistor.
The spacer layer can contain a non-doped (undoped) GaAs material or an undoped InP material, and the spacer layer can have a thickness of approximately 50 nm to 100 nm. However, the spacer layer can also have other dimensions.
In accordance with another configuration of the invention, the second layer is formed as a channel layer or as a channel of the field effect transistor, and the third layer formed on the second layer, i.e., on the channel layer, contains a wide-band-gap material, that is to say a material having a high energy band gap.
In the case where the third layer contains a wide-band-gap material, that is to say a material having a large energy band gap, the third layer can contain, for example, an Al0.3Ga0.7As material having a thickness of approximately 10 nm to 20 nm, or an Al0.48In0.52As material having a thickness of approximately 10 nm to 30 nm.
In accordance with another configuration of the invention, the channel layer contains a GaAs material, and the GaAs material of the channel layer is doped with an n-type dopant such as, e.g., silicon (Si).
In accordance with another configuration of the invention, the channel layer contains an In0.53Ga0.47As material, and the In0.53Ga0.47As material of the channel layer is doped with an n-type dopant such as, e.g., silicon (Si).
In accordance with another configuration of the invention, the n-doped channel layer, e.g. the n-doped GaAs channel layer or the n-doped In0.53Ga0.47As channel layer, has a high dopant concentration (n+-type doping).
By way of example, the n-doped (or n+-doped) channel layer can have a dopant concentration of approximately 0.5×1018 cm−3 to 5.0×1018 cm−3.
A GaAs channel layer formed on a GaAs spacer layer can have a thickness of approximately 20 nm to 50 nm, and an In0.53Ga0.47As channel layer formed on an InP spacer layer can have a thickness of approximately 10 nm to 30 nm. In alternative configurations, however, the channel layer can have other dimensions.
In accordance with another configuration of the invention, the cap layer contains a GaAs material, and the GaAs material of the cap layer is doped with an n-type dopant such as, e.g., silicon (Si).
In another configuration of the invention, the GaAs cap layer has a thickness of approximately 20 nm to 50 nm. However, the GaAs cap layer can also have other dimensions.
In accordance with another configuration of the invention, the cap layer has an In0.53Ga0.47As material, and the In0.53Ga0.47As material of the cap layer is doped with an n-type dopant such as, e.g., silicon (Si).
In another configuration of the invention, the In0.53Ga0.47As cap layer has a thickness of approximately 10 nm to 20 nm. However, the In0.53Ga0.47As cap layer can also have other dimensions.
In accordance with another configuration of the invention, the n-doped cap layer has a dopant concentration of approximately 1×1018 cm−3 to 5×1018 cm−3.
In accordance with another configuration of the invention, the fin structure (fin) has a width of approximately 25 nm to 50 nm. However, the width of the fin structure can also have other dimensions.
In accordance with another configuration of the invention, the gate region is formed using an electron beam lithography (EBL) method.
In another configuration of the invention, forming the gate region includes forming a gate recess.
The gate recess can be formed using a wet etching method or a dry etching method.
In accordance with another configuration of the invention, forming the gate region furthermore includes forming an insulating layer on the at least one partial region of the at least one sidewall of the fin structure and/or on the partial region of the upper surface of the third layer (e.g., the channel layer), and forming an electrically conductive layer on the insulating layer.
The electrically conductive layer can be formed using an electron beam evaporation method.
In alternative configurations of the invention, the channel layer can contain an InGaAs material or an InP material.
In accordance with one alternative configuration of the invention, the distance between the first source/drain region and the second source/drain region along the fin structure is approximately 2 μm to 3 μm. However, the distance can also have other dimensions.
In another configuration of the invention, the length of the gate region is approximately 30 nm to 100 nm. However, the length of the gate region can also have other dimensions.
In accordance with another configuration of the invention, the distance between the gate region and the first source/drain region is approximately 0.5 μm to 0.8 μm, and the distance between the gate region and the second source/drain region can likewise be approximately 0.5 μm to 0.8 μm. However, the distances mentioned above can also have other dimensions.
The electrically conductive layer of the gate region can comprise titanium (Ti) and/or platinum (Pt) and/or gold (Au). However, the electrically conductive layer can also contain other suitable, electrically conductive materials.
In accordance with another configuration of the invention, the first source/drain region and/or the second source/drain region are formed using a lithography method such as an optical lithography method, for example.
In accordance with another configuration of the invention, a first source/drain contact is formed on the first partial region of the cap layer for the purpose of making electrical contact with the first source/drain region, and a second source/drain contact is formed on the second partial region of the cap layer for the purpose of making electrical contact with the second source/drain region.
In another configuration of the invention, the first source/drain contact, which makes electrical contact with the first source/drain region, and the second source/drain contact, which makes electrical contact with the second source/drain region, comprise nickel (Ni) and/or germanium (Ge) and/or gold (Au).
To put it another way, nickel (Ni), germanium (Ge) or gold (Au) can be used for a source/drain metallization step during the formation of the first source/drain contact on the cap layer, more precisely on the first partial region of the cap layer, which forms the first source/drain region, and/or during the formation of the second source/drain contact on the cap layer, more precisely on the second partial region of the cap layer, which forms the second source/drain region. However, the first source/drain contact and/or the second source/drain contact can also contain other suitable, electrically conductive materials.
The first source/drain contact and/or the second source/drain contact can be formed on an upper surface of the cap layer, more precisely on an upper surface of the first source/drain region, which is formed from the first partial region of the cap layer, and on an upper surface of the second source/drain region, which is formed from the second partial region of the cap layer.
In accordance with another configuration of the invention, an anneal step or a thermal annealing step (e.g., a rapid thermal anneal (RTA)) is carried out after forming the first source/drain contact and/or after forming the second source/drain contact. By way of example, for GaAs-based FinFET/MuGFET devices, an anneal step can be carried out at a temperature of approximately 400° C. to 450° C., and for InGaAs/InP-based FinFETs/MuGFETs, an anneal step can be carried out at a temperature of approximately 300° C. to 350° C.
In another configuration of the invention, the fin structure is formed using an electron beam lithography (EBL) method and/or a dry etching method. In other words, the patterning of the second layer, of the third layer and of the cap layer for forming the fin structure can be realized using an EBL method and/or a dry etching method, which methods ensure, e.g., a sufficient accuracy for obtaining the desired fin structure dimensions.
In accordance with another configuration of the invention, a passivation layer is formed on at least one partial region of the cap layer and/or on at least one partial region of the third layer between the gate region and the first source/drain region and/or between the gate region and the second source/drain region.
The passivation layer can be formed using a growth method such as, for example, a plasma enhanced chemical vapor deposition (PECVD) method or a cathode sputtering method (sputter method) such as, for example, a DC sputter method or an RF sputter method, as is well known in the art.
The passivation layer can comprise a silicon nitride material (Si3N4 material). However, the passivation layer can also contain other suitable materials.
In accordance with another configuration of the invention, the passivation layer can have a thickness of approximately 50 nm to 150 nm. However, the thickness of the passivation layer can also have other dimensions.
Clearly, the passivation layer covers the gate-source interspace region and the gate-drain interspace region and insulates the devices.
Exemplary configurations of the invention are shown in the figures and are described thoroughly below. In the figures, similar or identical elements, in so far as is practical, are provided with similar or identical reference symbols. The illustrations shown in the figures are schematic and therefore not shown as true to scale.
In the figures:
The manufacturing of a compound semiconductor field effect transistor based on GaAs technology is described in accordance with the exemplary embodiment illustrated. The material combinations used are therefore specific to a GaAs material system. In alternative configurations of the invention, however, a compound semiconductor field effect transistor based on other compound semiconductor material systems, e.g., other III-V material systems, can be obtained by using other suitable material combinations.
The buffer layer 102 can be omitted in alternative configurations of the invention.
Clearly, in a finished field effect transistor device of the present invention, the third layer 105 serves as a channel layer 105, in other words as an electrically conductive channel 105, of the field effect transistor.
Clearly, the cap layer 106, or at least parts of the cap layer 106, serves for forming the source/drain regions 106a, 106b of the field effect transistor, see
In another process step of the method, using a standard photoresist mask such as, e.g., a standard positive resist mask, a lithography step (e.g., optical contact lithography) and a wet etching step, a mesa insulation is created, wherein a mesa structure 201 is formed by patterning the layer arrangement 100 with the aid of wet etching of the layer arrangement 100 down to the buffer layer 102, i.e., down to the upper surface of the buffer layer 102, as is illustrated in
In alternative configurations of the invention, the wet etching of the layer arrangement 100 can be stopped at the upper surface of the first layer 103 (i.e., of the barrier layer 103) or at the upper surface of the substrate 101.
The wet etching step can be carried out using a wet etching solution of H2SO4:H2O2:H2O (4:1:35), and by etching for a time duration of approximately 30 s to 40 s.
In another configuration of the invention, such as, for example, in the case of indium phosphide/indium gallium arsenide (InP/InGaAs) based FinFETs or MuGFETs, other wet etching solutions can be used such as, for example, H3PO4:H2O2:H2O (1:1:25) for wet etching with a time duration of approximately 30 s to 40 s for the mesa insulation.
In another process step of the method, a fin structure 210 having a rectangular cross section is formed by patterning the second layer 104 (spacer layer 104), the third layer 105 (channel layer 105) and the cap layer 106, as is illustrated in
The fin 210 can be formed using an electron beam lithography (EBL) method and a dry etching method. In the context of this process step, firstly a thin silicon nitride layer (Si3N4 layer) can be formed as a mask on the cap layer 106 (e.g., by deposition), for example, with a thickness of approximately 50 nm, and afterward an electron-sensitive resist material (electron beam resist) can be applied to the mask (e.g., by spin-coating). The wafer can subsequently be exposed by means of an electron beam and then developed.
The silicon nitride material can be etched away, such that only the fin surface remains as mask. The rectangular fin 210 can be obtained by dry etching. The width of the fin 210 obtained can vary from approximately 25 nm to 50 nm.
A first source/drain contact 107a is formed on a first partial region of the cap layer 106, and a second source/drain contact 107b is formed on a second partial region of the cap layer 106.
The definition of the source/drain contacts can be achieved by optical lithography and a lift-off method.
The distance Lsd between the first source/drain contact 107a and the second source/drain contact 107b can be approximately 1 μm to 3 μm, see
The first source/drain contact 107a and the second source/drain contact 107b can each have a layer arrangement comprising a nickel layer (Ni layer) having a thickness of approximately 18 nm, a germanium layer (Ge layer) arranged on the Ni layer and having a thickness of approximately 50 nm, and a gold layer (Au layer) arranged on the Ge layer and having a thickness of approximately 150 nm.
The materials (i.e., the metals) used for the source/drain contacts 107a, 107b are, for example, well suited to GaAs-based or InGaAs/InP-based FinFET devices or MuGFET devices. The metals can be deposited, for example, with the aid of an electron beam evaporation method, as is well known in the art.
In addition to the source/drain metallization, a rapid thermal anneal can be effected, e.g., at 400° C. to 450° C. for GaAs-based FinFET/MuGFET devices or at 300° C. to 350° C. for InGaAs/InP-based FinFETs/MuGFETs.
Referring to
Firstly, a gate lithography step can be performed, e.g., by depositing a layer composed of an electron-sensitive resist material on the cap layer 106 and by subsequent exposure by means of an electron beam. After development of the electron-sensitive resist and prior to a gate metallization evaporation step, the cap layer 106 can be subjected to wet etching, such that the gate 108 is formed directly on the third layer 105 (i.e., the GaAs channel layer 105).
To put it another way, a gate recess is formed, e.g., by using an electron beam lithography (EBL) process step and a wet etching process step and/or a dry etching process step for uncovering the upper surface of the underlying channel layer 105, or, more precisely, the upper surface of that partial region of the channel layer 105 which lies below the removed partial region of the cap layer 106.
After the gate recess has been formed, the cap layer 106 has been removed in the region of the field effect transistor, which region will later become the gate region of the field effect transistor. The remaining partial regions of the cap layer 106, that is to say a first partial region 106a of the cap layer 106 and a second partial region 106b of the cap layer 106, correspondingly form a first source/drain region 106a and a second source/drain region 106b of the field effect transistor.
The wet etching of the cap layer 106 can be effected using a citric acid:H2O2:H2O (25:1:75) etching solution at room temperature. Since a wet-etching etchant is used, the cap layer 106 can be etched away isotropically (along the vertical and the horizontal direction), such that lateral interspaces 109 can be manufactured between the gate 108 and the source/drain regions 106a, 106b. In this way, the gate 108 can be spatially (physically) insulated from the cap layer 106 (i.e., the first source/drain region 106a and the second source/drain region 106b), and what can be achieved is that the gate 108 is situated only on the upper surface of the GaAs channel 105 and along the sidewalls of the body of the fin structure 210. This produces a tri-gate field effect transistor (tri-gate FET) or a so-called multi-gate field effect transistor (MuGFET).
What can be achieved in another configuration of the invention is that the gate 108 is formed only on (or along) the sidewalls of the body of the fin 210, such that a double-gate device or a fin field effect transistor (FinFET) is obtained. In this case, the partial region of the upper surface of the fin structure 210, which partial region is situated between the first source/drain region 106a and the second source/drain region 106b, in other words the uncovered upper surface of the channel layer 105, can be passivated prior to the gate metallization, e.g., with a silicon nitride layer (Si3N4 layer).
After the gate lithography and the etching of the cap layer 106, gate metals are evaporated, for example, with the aid of an electron beam evaporation technique. Suitable gate metals for GaAs-based and InGaAs/InP-based FinFETs/MuGFETs can have a Ti/Pt/Au (20/10/350 nm) layer arrangement, that is to say a layer composed of titanium (Ti) having a thickness of approximately 20 nm, a layer composed of platinum (Pt) and arranged on the Ti layer and having a thickness of approximately 10 nm, and a layer composed of gold and arranged on the Pt layer and having a thickness of approximately 350 nm. Another combination of gate metals may be a Pt/Ti/Pt/Au (8/20/10/350 nm) layer arrangement, that is to say an 8 nm thick first Pt layer, a 20 nm thick Ti layer arranged on the first Pt layer, a 10 nm thick second Pt layer arranged on the Ti layer, and a 350 nm thick Au layer arranged on the second Pt layer.
A compound semiconductor field effect transistor having a fin structure (e.g., a FinFET or a MuGFET) which is manufactured in accordance with an exemplary embodiment of the invention can be normally on or normally off, depending on the threshold voltage of the device (field effect transistor), which threshold voltage optionally depends on the thickness of the fin structure 210, the fin height and the doping in the body of the fin 210.
A two-dimensional cross-sectional view of an exemplary device structure of a compound semiconductor field effect transistor 100 is illustrated in
Another exemplary embodiment of a compound semiconductor field effect transistor structure 300 is illustrated in
Furthermore, the field effect transistor 300 has a third layer 305 formed on the second layer 304 (channel layer 304). The third layer 305 contains an Al0.3Ga0.7As material having a high energy band gap (wide-band-gap Al0.3Ga0.7As material).
Clearly, in the exemplary embodiment shown in
The thickness of the Al0.3Ga0.7As wide-band-gap layers 303, 305 can be in each case approximately 10 nm to 20 nm, and the thickness of the channel layer 304 can likewise be approximately 10 nm to 20 nm. The thickness of the cap layer (represented by the first source/drain region 306a and the second source/drain region 306b) can be approximately 20 nm to 40 nm.
The cap layer, that is to say the first source/drain region 306a formed from the cap layer and the second source/drain region 306b formed from the cap layer, is formed as an n-doped GaAs layer having a dopant concentration of approximately 1×1018 cm−3 to 5×1018 cm−3.
The process sequence for the production of the field effect transistor 300 is the same as the one described for the field effect transistor 100 with reference to
After the growth of the buffer layer 402, a first layer 403 (also referred to as barrier layer 403) containing an undoped wide-band-gap Al0.48In0.52As material is formed (grown) on the buffer layer 402 in order to effectively suppress the charge carrier transport into the substrate 401 by creating a potential barrier. A layer thickness of approximately 100 nm to 500 nm can suffice to minimize the growth time of the barrier layer 403 and nevertheless to provide an effective barrier.
After the growth of the first layer 403, a second layer 404 is grown, which second layer 404 contains an undoped InP material. The second layer 404 can have a thickness of approximately 50 nm to 100 nm and is also referred to as a spacer layer 404.
After the growth of the second layer 404 (spacer layer 404), a third layer 405 containing a highly doped (e.g., n+-doped with a dopant concentration of approximately 0.5×1018 cm−3 to 5.0×1018 cm−3) In0.53Ga0.47As material is formed (grown) with a thickness of approximately 10 nm to 30 nm on the second layer 404. The third layer 405 serves as a channel layer 405 of the field effect transistor 400.
The compound semiconductor field effect transistor 400 having the fin structure 210 is completed by a final 10 nm to 20 nm n-doped (dopant concentration of approximately 1×1018 cm−3 to 5×1018 cm−3) In0.53Ga0.47As cap layer, represented in
The complete layer sequence shown in
In an alternative configuration of the invention, the InGaAs channel layer 405 can be replaced by a doped InP channel layer. In this way, the field effect transistor 400 can be tailored both to applications requiring a high speed (high-speed application) and to applications requiring a high power (high-power applications). The process sequence is the same as described above.
In accordance with another exemplary embodiment of the invention, an undoped wide-band-gap Al0.48In0.52As Schottky contact layer can be inserted directly below the gate region 108 and on the doped channel layer (n+-doped with a dopant concentration of approximately 0.5×1018 cm−3 to 5.0×1018 cm−3)composed of In0.53Ga0.47As material. The resulting field effect transistor structure 500 is shown in
One advantage of the arrangement shown in
The indium proportion (indium content) in the In0.53Ga0.47As channel layer 504 can be varied from x=0.53 to x=0.7 in order to increase the electron mobility even further and, consequently, to obtain better high-speed performance. In this case, the maximum thickness of the channel layer 504 is restricted on account of strain produced (induced) in the channel layer 504 since the channel layer 504 is no longer lattice-matched to the InP substrate 401.
Number | Date | Country | Kind |
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10 2005 059 231.7 | Dec 2005 | DE | national |
This application is a continuation of co-pending International Application No. PCT/DE2006/002221, filed Dec. 12, 2006, which designated the United States and was not published in English, and which is based on German Application No. 10 2005 059 231.7 filed Dec. 12, 2005, both of which applications are incorporated herein by reference.
Number | Date | Country | |
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Parent | PCT/DE2006/002221 | Dec 2006 | US |
Child | 12128239 | US |