“Asymmetric Source/Drain Extension Transistor Structure for High Performance Sub-50nm Gate Length CMOS Devices,” T. Ghani, K. Mistry, P. Packan, M. Armstrong, S. Thompson, S. Tyagi, M. Bohr, Portland Technology Development, TCAD, Intel Corporation, Hillsboro (2001 Symposium on VLSI Technology Digest of Technical Papers, p. 17). |
“Asymmetrically-Doped Buried Layer (ADB) Structure for Low-Voltage Mixed Analog-Digital Applications,” Masafumi Miyamoto, Kenji Toyota, Koichi Seki, and Takahiro Nagano, Semiconductor Development Center, Central Research Laboratory, Hitachi, Ltd. 1-280, Higashi-koigakubo, Kokubuni, Tokyo 185, Japan (1996 Symposium on VLSI Technology Digest of Technical Papers, p. 102). |
“Graded Gate VDMOSFET,” Shuming Xu, Kian Paau Gan, Pang Dow Foo, Yi Su, and Yong Liu (IEEE Electron Device Letters, vol. 21, No. 4, Apr. 2000). |
“Lateral Thinking About Power Devices (LDMOS),” Taylor R. Efland, Chin-Yu Tsai, Sameer Pendharkar (Power Device Development, Mixed Signal Productization, Texas Instruments Incorporated, Dallas, Texas, USA). |
“RF LDMOSFET with Graded Gate Structure,” Xu, Shuming, and Foo, Pan Dow (Institute of Microelectronics, 10 Science Park Road, #02-19/26 (The Alpha, Singapore Science Park II, Singapore 117684, p. 221). |
“Transistor Design Issues in Integrating Analog Functions with High Performance Digital CMOS,” A. Chatterjee, K. Vasanth, D. T> Grider, M. Nandakumar, G. Pollack, R. Aggarwal, M. Rodder and H. Schichijo (Silicon Technology Development, Texas Instruments, Dallas, USA, p. 11A-1). |