Claims
- 1. A method for manufacturing an interconnection structure interconnecting conductive layers provided in a semiconductor substrate, said method comprising the process steps of:
- (a) providing a first conductive layer on an upper surface of a substrate, said first conductive layer is connected to an internal circuit formed in arbitrary region on said substrate;
- (b) forming a first insulating layer on an upper surface of said first conductive layer;
- (c) providing a multi-layer structure on an upper surface of said first insulating layer, said multi-layer structure having:
- second conductive layers provided in parallel to said upper surface of said substrate and connected respectively to internal circuits formed in an arbitrary region on said substrate,
- at least one second insulating layer inserted between said second conductive layers for insulating said second conductive layers from each other, and
- a third insulating layer provided in a top of said multi-layer structure;
- (d) selectively removing said multi-layer structure to form a recess in said multi-layer structure, said recess reaching said upper surface of said first insulating layer;
- (e) forming a side wall covering a side surface of said multi-layer structure which defines a side surface of said recess, where said side wall includes an insulating film existing at least in a surface region of said side wall facing a center of said recess, and said side wall also contacts an outer part of a bottom surface of said recess which is a part of said upper surface of said first insulating layer;
- (f) selectively removing a part of said first insulating layer existing under said recess to expose a contact region being a part of said first conductive layer: and
- (g) forming a third conductive layer in said recess and on an upper surface of said third insulating layer, thereby to interconnect said first conductive layer and an internal circuit provided in an arbitrary region on said substrate which is connected to said third conductive layer at a place out of said recess.
- 2. A method in accordance with claim 1, wherein
- said process step (e) have the process steps of:
- (e-1) providing a conductive material layer in said recess and on an upper surface of said third insulating layer, said conductive material layer having an upper surface caving in said recess;
- (e-2) selectively etching said conductive material layer to form a conductive wall contacting only both said side surface of said multi-layer structure and said outer part of said bottom surface; and,
- (e-3) forming said insulating film on said surface region of said conductive wall thereby to obtain said side wall having said insulating film and said conductive wall as a connection wall for electrically interconnecting said second conductive layers in a vertical direction.
- 3. A method in accordance with claim 2, wherein
- said process step (e-2) is performed by an anistotropic etching of said conductive material layer whose etching rate in a vertical direction is greater than that in a lateral direction.
- 4. A method in accordance with claim 1, wherein
- said conductive material layer is made of silicon,
- a whole region of said side wall is provided as said insulating film, and
- said step (e) have the steps of:
- (e-11) providing a conductive material layer in said recess and on an upper surface of said third insulating layer, said conductive material layer having an upper surface caving in said recess;
- (e-12) selectively etching said conductive material layer to form a conductive wall contacting only both said side surface of said multi-layer structure and said outer part of said bottom surface; and
- (e-13) transforming a whole region of said conductive wall to said insulating film by oxiding said conductive wall.
Parent Case Info
This is a division, of application Ser. No. 07/168,386, filed on Mar. 15, 1988, U.S. Pat. No. 4,872,050.
US Referenced Citations (5)
Non-Patent Literature Citations (2)
Entry |
"A VLSI Bipolar Metallization Design . . . ", IBM J. Res. Develop., vol. 26, No. 3, May 1982, pp. 362-371. |
"VLSI Multilevel Metallization", Solid State Technology, Dec. 1984, pp. 93-100. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
168386 |
Mar 1988 |
|