This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-153997, filed on Sep. 14, 2020; the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a method for manufacturing a semiconductor device and a semiconductor device.
It is desirable to design a device in which a gate electrode that is located in a trench controls a channel that conducts a current in the vertical direction of a semiconductor layer by performing the device design after improving the trade-off between the on-resistance and the parasitic capacitance that occurs due to the positional relationship between the gate electrode and the base region. It is also desirable to suppress the fluctuation of the on-resistance and capacitance that may occur in the actual device due to fluctuation when manufacturing.
According to one embodiment, a method for manufacturing a semiconductor device includes forming a trench in a first semiconductor layer of a first conductivity type; filling a first insulating film into the trench; etching the first insulating film to cause an upper surface of the first insulating film to recede lower than an opening of the trench and to expose a sidewall of an upper portion of the trench from under the first insulating film; forming a second-conductivity-type semiconductor region in a region of the first semiconductor layer next to the upper portion of the trench by implanting a second-conductivity-type impurity through the sidewall of the upper portion of the trench into the first semiconductor layer and by diffusing the second-conductivity-type impurity; and forming a gate electrode on the first insulating film in the upper portion of the trench after the forming of the second-conductivity-type semiconductor region.
Embodiments will now be described with reference to the drawings. The same components in the drawings are marked with the same reference numerals.
Although the first conductivity type is described as an n-type and the second conductivity type is described as a p-type in embodiments described below, the first conductivity type may be the p-type; and the second conductivity type may be the n-type.
The semiconductor device 1 includes a semiconductor part 10, a drain electrode (a first electrode) 51, a source electrode (a second electrode) 52, a gate electrode (a control electrode) 30, and a field plate electrode 20. The drain electrode 51 is located at one surface of the semiconductor part 10; and the source electrode 52 is located at the other surface of the semiconductor part 10. The semiconductor device 1 is a vertical semiconductor device in which a current is caused to flow in a direction (the vertical direction) connecting the drain electrode 51 and the source electrode 52 by the control of the gate electrode 30.
The material of the semiconductor part 10 is, for example, silicon. Or, the material of the semiconductor part 10 may be, for example, silicon carbide, gallium nitride, etc.
The semiconductor part 10 includes an n+-type drain layer (or substrate) 11, an n-type drift layer (a first semiconductor layer) 12, a p-type base region (a second-conductivity-type semiconductor region) 13, and an n+-type source region (a first-conductivity-type semiconductor region) 14.
The drift layer 12 is located on the drain layer 11. The n-type impurity concentration of the drain layer 11 and the n-type impurity concentration of the source region 14 are greater than the n-type impurity concentration of the drift layer 12. The base region 13 is located on the drift layer 12; and the source region 14 is located on the base region 13.
Multiple trenches T are formed in the semiconductor part 10. The sidewalls of the trenches T are next to the source region 14, the base region 13, and the drift layer 12. The bottoms of the trenches T are positioned in the drift layer 12.
As shown in
As shown in
The gate electrode 30 is next to a portion of the source region 14 and a portion of the base region 13 with a gate insulating film 43 interposed. The gate insulating film 43 is located between the gate electrode 30 and the source region 14 and between the gate electrode 30 and the base region 13.
The base region 13 faces the side surface of the gate electrode 30 via the gate insulating film 43. An n-type channel (an inversion layer) can be formed in the portion of the base region 13 that faces the gate electrode 30 by applying a voltage that is not less than a threshold to the gate electrode 30.
The base region 13 includes a first portion 13a and a second portion 13b. The first portion 13a is positioned between the gate insulating film 43 and the second portion 13b and contacts the gate insulating film 43. The first portion 13a is next to the gate insulating film 43 (the sidewall of the trench T). The p-type impurity concentration of the first portion 13a is greater than the p-type impurity concentration of the second portion 13b.
According to the first embodiment, the boundary between the first portion 13a and the gate insulating film 43 protrudes lower than the second portion 13b. The lowermost end of the base region 13 is positioned at the boundary between the first portion 13a and the gate insulating film 43. The lowermost end of the base region 13 is positioned lower than the lowermost end of the gate electrode 30.
The drain electrode 51 is located at the back surface of the drain layer 11. The drain electrode 51 contacts the drain layer 11 and is electrically connected with the drain layer 11.
The source electrode 52 is located on the upper surface of the semiconductor part 10. The source electrode 52 contacts the upper surface and side surface of the source region 14 and is electrically connected with the source region 14. Also, the source electrode 52 contacts the base region 13 and is electrically connected with the base region 13. The p-type impurity concentration of the portion of the base region 13 that contacts the source electrode 52 is greater than the p-type impurity concentration of the first portion 13a and the p-type impurity concentration of the second portion 13b.
An insulating film 44 is located between the source electrode 52 and the gate electrode 30. The gate electrode 30 is electrically connected with a not-illustrated gate interconnect. For example, the field plate electrode 20 is electrically connected with the source electrode 52. The field plate electrode 20 relaxes the distribution of the electric field of the drift layer 12 in the gate off-state.
A method for manufacturing the semiconductor device 1 of the first embodiment will now be described with reference to
As shown in
As shown in
A space that is surrounded with the insulating film 41 above the field plate electrode 20 in the trench T is ensured. The insulating film 42 shown in
When forming the insulating film 42, the upper surface of the insulating film 42 is positioned higher than the opening of the trench T. Subsequently, the upper surface of the insulating film 42 is caused to recede by etching the insulating film 42. As shown in
The gate insulating film 43 is formed at the exposed sidewall of the upper portion of the trench T as shown in
After forming the gate insulating film 43, a p-type impurity is implanted by ion implantation through the sidewall of the upper portion of the trench T into the semiconductor part 10 (the drift layer 12). The p-type impurity is implanted into the drift layer 12 through the gate insulating film 43. The p-type impurity is, for example, boron. In
As shown in the plan view of
After the ion implantation as shown in
The conductive body that is used as the material of the gate electrode 30 is formed on the semiconductor part 10 so that the upper surface of the conductive body is positioned higher than the opening of the trench T; subsequently, the upper surface of the gate electrode 30 is caused to recede lower than the opening of the trench T. The upper surface of the gate electrode 30 is positioned in the trench T to be lower than the opening of the trench T.
After forming the gate electrode 30, an n-type impurity is implanted through the upper surface of the semiconductor part 10 into the semiconductor part 10. The n-type impurity is implanted in a direction that is substantially perpendicular to the upper surface of the semiconductor part 10. The n-type impurity is, for example, phosphorus or arsenic.
Subsequently, the p-type impurity and the n-type impurity that are implanted into the semiconductor part 10 are diffused by heat treatment. Thereby, as shown in
The insulating film 44 is filled into the trench T on the gate electrode 30. The insulating film 44 is formed to cover the upper surface of the semiconductor part 10; subsequently, the insulating film 44 that is on the upper surface of the semiconductor part 10 (the upper surface of the source region 14) is removed. At this time, the gate insulating film 43 that is formed at the upper surface of the source region 14 also is removed; and the upper surface of the source region 14 is exposed.
A contact trench that reaches the base region 13 from the exposed upper surface of the source region 14 is formed; subsequently, the source electrode 52 is formed in the contact trench and on the semiconductor part 10. The drain electrode 51 is formed at the back surface of the drain layer 11.
The gate electrode 30 of
According to embodiments, the p-type impurity is implanted through the sidewall of the upper portion of the trench T into the drift layer 12 (the process of
As shown in
As shown in
The solid line illustrates the characteristic when the protrusion amount of the deepest portion (the portion next to the sidewall of the trench T) with respect to the shallowest portion of the lower surface of the base region 13 was 0.100 μm.
The dashed line illustrates the characteristic when the protrusion amount of the base region 13 described above was 0.050 μm.
The dotted line illustrates the characteristic when the protrusion amount of the base region 13 described above was 0.020 μm.
The single dot-dash line illustrates the characteristic when the protrusion amount of the base region 13 described above was 0.010 μm.
The double dot-dash line illustrates the characteristic when the protrusion amount of the base region 13 described above was 0.001 μm.
The position of the shallowest portion of the lower surface of the base region 13 was the same for these five cases.
It can be seen from the simulation results of
The protrusion amount of the portion of the base region 13 next to the sidewall of the trench T can be adjusted by controlling the ion implantation conditions of the p-type impurity implanted through the sidewall of the trench T into the drift layer 12 such as the implantation angle, the acceleration, etc. Also, the protrusion amount of the portion of the base region 13 next to the sidewall of the trench T can be adjusted by implanting the p-type impurity multiple times while changing the angle and/or the velocity.
For example, by increasing the acceleration of the p-type impurity, the lower surface of the base region 13 can be substantially flat as shown in
As shown in
This structure is formed by performing additional etching of the insulating film 42 to cause the upper surface of the insulating film 42 to recede lower than the lower end of the base region 13 as shown in
The trench T that includes the gate electrode 30 in the interior of the trench T is not limited to stripe-shaped and may be a polygonal hole that includes three or more sidewalls.
In such a case as well, even if the position of the lower end of the gate electrode 30 fluctuates, the distance in the vertical direction (the current path direction) between the lower end of the gate electrode 30 and the lower end of the base region 13 can be substantially constant, and a robust structure can be realized in which the device characteristics are not sensitive to the fluctuation when manufacturing.
The field plate electrode 20 is located along the central-axis direction of the trench T at the center position of the trench T. The gate electrode 30 surrounds the perimeter of the upper portion of the field plate electrode 20 in the upper portion of the trench T. An insulating film 45 is located between the field plate electrode 20 and the gate electrode 30.
The insulating film 44 is located on the field plate electrode 20 and on the gate electrode 30 in the trench T. An insulating film 46 is located on the semiconductor part 10 and on the insulating film 44. The source electrode 52 is located on the insulating film 46.
The field plate electrode 20 is connected with the source electrode 52 via a metal plug 61 that extends through the insulating film 46 and the insulating film 44.
As shown in
As shown in
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.
Number | Date | Country | Kind |
---|---|---|---|
2020-153997 | Sep 2020 | JP | national |