The present invention relates to a method for manufacturing a semiconductor device having a hollow hermetic sealing structure.
High-frequency semiconductor devices such as field-effect transistor elements using compound semiconductors like GaAs and GaN are rapidly being generalized and there is a strong demand for cost reduction. In order to respond to this demand, instead of totally sealed metal packages which have been used so far, low-priced mold packages are being adopted. However, when adopting non-sealed packages like mold packages, it is necessary to secure moisture resistance of semiconductor devices in order to prevent various kinds of deterioration attributable to moisture. For this reason, there is a demand for manufacturing semiconductor devices having a hollow hermetic sealing structure in which only necessary parts are sealed.
In conventional semiconductor devices, an insulating lid is bonded to a ceramic substrate on which a semiconductor element is mounted using glass to seal the semiconductor element (e.g., see Patent Literature 1). In this device, a dielectric constant of glass is 15 or below, a dielectric constant of the insulating lid is 15 or below and a difference in thermal expansion among the ceramic substrate, glass and lid is 1.2×10−6/° C. or below.
Patent Literature 1: Japanese Patent No. 3566508 (p. 3, lines 35 to 46, FIG. 1)
Semiconductor elements are conventionally sealed with an insulating lid one by one. For this reason, there has been a problem that despite a high-degree of air tightness, productivity is low and manufacturing cost is high.
The present invention has been implemented to solve the above-described problem, and it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of reducing manufacturing cost while securing air tightness.
A method for manufacturing a semiconductor device according to the present invention includes: forming a plurality of semiconductor elements on a first substrate; forming a plurality of sealing windows and a support portion supporting the plurality of sealing windows on a second substrate; pressing the second substrate against the first substrate by using a pressurizing member and bonding the plurality of sealing windows of the second substrate to the first substrate via a low melting point glass member arranged around the plurality of semiconductor elements; and separating the support portion from the plurality of sealing windows bonded to the first substrate.
The present invention makes it possible to reduce manufacturing cost while securing air tightness.
A method for manufacturing a semiconductor device according to the embodiments of the present invention will be described with reference to the drawings. The same components will be denoted by the same symbols, and the repeated description thereof may be omitted.
An electrode pad 3 is electrically connected to the semiconductor element 2. Examples of the electrode pad 3 include a gate pad, source pad and drain pad. The semiconductor element 2 is covered with a surface protective film 4 such as an SiN film formed by means of plasma CVD or the like. A back pad 5 is provided on the back surface of the substrate 1 and electrically connected to the electrode pad 3 via a through electrode 6 that penetrates the substrate 1. Although the back pad 5 is used here, without being limited to this, field-through wiring may also be used.
A low melting point glass member 7 is disposed around the sealed area including the semiconductor element 2 on the substrate 1. A sealing window 8 is bonded to the substrate 1 via the low melting point glass member 7 to seal the semiconductor element 2. The low melting point glass member 7 is made of, for example, vanadium-based glass. The vanadium-based glass can be baked at 450° C. or below, has a high moisture-resistant material characteristic and has a black color tone. Bismuth-based glass, lead-based glass, lead fluorine-based glass or the like capable of baking at 400° C. or below may be used as the low melting point glass member 7.
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
First, as shown in
Next, as shown in
Next, as shown in
Here, the low melting point glass member 7 is applied to the substrate 1, but it may also be applied to the sealing window 8. In that case, the low melting point glass member 7 is provisionally baked on the SOI substrate 12 including the sealing window 8. The low melting point glass member 7 is applied before forming the support portion 13. However, when the support portion 13 has sufficient strength, the low melting point glass member 7 may be applied after forming the support portion 13.
Next, as shown in
Moreover, the support portions 13 are broken by pressurizing the entire surface of the SOI substrate 12 by the pressurizing member 14 at several MPa to several tens of MPa. As shown in
Since the semiconductor element 2 is sealed with the low melting point glass member 7 and the sealing window 8 in the present embodiment, air tightness can be secured. The plurality of semiconductor elements 2 on the substrate 1 are collectively sealed with the plurality of sealing windows 8 integrated with the SOI substrate 12 in a wafer state, making it possible to improve productivity and reduce manufacturing cost.
Furthermore, when the plurality of sealing windows 8 are bonded to the substrate 1, the low melting point glass members 7 are selectively heated and melted using far-infrared rays. In this way, it is possible to melt the low melting point glass member 7 while avoiding an excessive temperature rise of the semiconductor element 2, and thereby secure excellent moisture resistance with respect to the semiconductor element 2. For example, even if the heat-resisting temperature of the semiconductor element 2 is merely on the order of 250° C., it is possible to prevent thermal destruction.
The low melting point glass member 7 has a higher far-infrared ray absorption rate than the semiconductor element 2 and sealing window 8. Thus, even when the entire substrate is irradiated with far-infrared rays, it is possible to selectively heat the low melting point glass member 7 without causing a temperature rise of the semiconductor element 2 having a low absorption rate. For example, Si allows nearly 60% of far-infrared rays having a wavelength of 3 μm to 5 μm to pass therethrough, while carbon absorbs approximately 90% of far-infrared rays. When a difference in the far-infrared ray absorption rate between the black vanadium-based low melting point glass member 7 and the substrate 1 is on the order of 40%, it is possible to selectively heat the low melting point glass member 7.
Table 1 illustrates Young's moduli and thermal expansion coefficients of various materials. Table 2 illustrates amounts of curvature [μm] measured when strip-shaped substrates (length 4 mm, thickness 0.1 mm) of various materials are pasted to each other, one side thereof is fixed and the temperature is changed by 200 degrees.
Since materials having amounts of curvature exceeding 50 μm cannot be used due to mounting-related problems or the like, the difference in coefficient of linear expansion between the sealing window 8 and the substrate 1 needs to be 4.3×10−6 [/K] or below. For example, when the substrate 1 is Si, the material of the sealing window 8 may be glass or the like which is similar to Si in a coefficient of linear expansion, but producing the sealing window 8 using Si as with the substrate 1 is more preferable because this can reduce the problem related to curvature or the like even when the thickness of the substrate 1 is reduced. The same applies to cases where the substrate 1 is a semiconductor substrate such as SiC, GaAs, GaN or an insulating substrate such as sapphire, ceramic. Therefore, the material of the sealing window 8 is preferably the same as the material of the substrate 1 or a material whose difference in coefficient of linear expansion from the substrate 1 is 4.3×10−6 [/K] or below.
As shown in
Next, as with Embodiment 1, a plurality of semiconductor elements 2 are formed on the substrate 1, and the plurality of semiconductor elements 2 are subjected to provisional baking with the low melting point glass member 7 applied therearound.
Next, as shown in
As with Embodiment 1, the present embodiment can reduce manufacturing cost while securing air tightness. By selectively heating and melting the low melting point glass member 7 using far-infrared rays, it is possible to melt the low melting point glass member 7 while avoiding an excessive temperature rise of the semiconductor element 2.
As shown in
In this case, the support portions 13 are broken by causing the protrusion 18 of the pressurizing member 17 to pressurize the sealing window 8 of the substrate 16. An unnecessary portion 21 after the cutting are suctioned by the suctioning mechanism 19 and removed. The suctioning mechanism 19 performs suctioning or the like using vacuum suctioning, an adhesive member or gel substance. The support portions 13 may be broken by pressurizing the unnecessary portion 21 around the sealing window 8.
The low melting point glass member 7 is selectively irradiated and melted with far-infrared rays via the opening 20 of the pressurizing member 17. The protrusion 18 for pressurizing also has a role of covering the substrate 1 from far-infrared rays and preventing a temperature rise. It is thereby possible to prevent an excessive temperature rise of the semiconductor element 2 even when the substrate 1 has a high far-infrared ray absorption rate. Other steps and effects are the same as those in Embodiments 1 and 2.
In the present embodiment, the low melting point glass member 7 is selectively irradiated with far-infrared rays using the pressurizing member 17 as a mask, but the substrate 16 may be configured to have a lens shape (not shown) and the low melting point glass member 7 may be selectively irradiated with far-infrared rays. Moreover, the pressurizing member 17 may be coated with a reflection film so as to cover regions other than the low melting point glass member 7.
1 substrate (first substrate); 2 semiconductor element; 7 low melting point glass member; 8 sealing window; 9 first Si layer; 10 SiO2 layer; 11 second Si layer; 12 SOI substrate (second substrate); 13 support portion; 14, 17 pressurizing member; 16 substrate (second substrate); 20 opening
Number | Date | Country | Kind |
---|---|---|---|
2012-205771 | Sep 2012 | JP | national |
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/JP2013/069669 | 7/19/2013 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
---|---|---|---|
WO2014/045701 | 3/27/2014 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
20040061207 | Ding | Apr 2004 | A1 |
Number | Date | Country |
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10 27860 | Jan 1998 | JP |
3566508 | Sep 2004 | JP |
2006 501679 | Jan 2006 | JP |
4385145 | Dec 2009 | JP |
4619201 | Jan 2011 | JP |
2011 220938 | Nov 2011 | JP |
175564 | Dec 1991 | TW |
2012 120694 | Sep 2012 | WO |
Entry |
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International Preliminary Report on Patentability and Written Opinion issued Apr. 2, 2015 in PCT/JP2013/069669 (English translation only). |
Combined Office Action and Search Report issued Apr. 20, 2015 in Taiwanese Patent Application No. 102131955 (with partial English translation of the Office Action and English translation of categories of cited documents). |
International Search Report Issued Oct. 22, 2013 in PCT/JP13/069669 Filed Jul. 19, 2013. |
Japanese Office Action issued Mar. 15, 2016 in Patent Application No. 2014-536651 (with partial English translation). |
Number | Date | Country | |
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20150243530 A1 | Aug 2015 | US |