Patent Application
20230276577
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2022-029881, filed Feb. 28, 2022, the entire contents of which are incorporated herein by reference.
The present invention relates to a method for manufacturing a wiring substrate.
Japanese Patent Application Laid-Open Publication No. 2017-11092 describes a conduction inspection method for a printed wiring board having a buildup layer. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a method for manufacturing a wiring substrate includes preparing a first support plate having a metal foil formed on a surface of a support substrate, forming a wiring substrate on the metal foil of the first support plate such that the wiring substrate has a first surface facing the metal foil of the first support plate, attaching a second support plate to a second surface of the wiring substrate on the opposite side with respect to the first surface, and separating the support substrate from the metal foil of the first support plate after the attaching of the second support plate such that the metal foil of the first support plate is removed from the first surface of the wiring substrate and that the first surface of the wiring substrate is exposed. The wiring substrate has first conductor pads formed on the first surface, and second conductor pads formed on the second surface, and the method for manufacturing the wiring substrate includes conducting a first conduction inspection such that conduction between the second conductor pads is inspected before the attaching of the second support plate to the second surface of the wiring substrate, and conducting a second conduction inspection such that conduction between the first conductor pads is inspected after the removing of the metal foil from the first surface of the wiring substrate.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
A method for manufacturing a wiring substrate according to an embodiment of the present invention is described with reference to the drawings. First, as illustrated in
A surface of the carrier metal foil layer (11a) on an opposite side with respect to the metal foil layer (11b) is bonded to a surface of the support substrate 10 by thermocompression bonding or the like. The metal foil layer (11b) and the carrier metal foil layer (11a) are adhered to each other, for example, with a separable adhesive such as a thermoplastic adhesive. That is, the metal foil 11 has a structure including two layers, a first layer (carrier metal foil layer) (11a) and a second layer (metal foil layer) (11b), which are separable from each other. The metal foil layer (11b) and the carrier metal foil layer (11a) may be adhered to each other only near an outer periphery thereof in an extension direction (planar direction) in a plan view.
As the first support plate 100, a double-sided copper-clad laminated plate may be used. As the metal foil layer (11b) and the carrier metal foil layer (11a) that form the metal foil 11, copper foils are preferably used. However, without being limited to this, other metal foils such as nickel foils may also be used. In the example illustrated in
In the following description referring to
In the description of the method for manufacturing a wiring substrate of the present embodiment, a side farther from the support substrate 10 of first support plate 100 is referred to as “upper,” “upper side,” “outer side,” or “outer,” and a side closer to the support substrate 10 is referred to as “lower,” “lower side,” “inner side,” or “inner.” Further, for each structural element, a surface facing an opposite side with respect to the support substrate 10 is also referred to as an “upper surface,” and a surface facing the support substrate 10 is also referred to as a “lower surface.” Therefore, in the description of each element formed on an upper side of the metal foil 11, a side farther from the first support plate 100 is also referred to as an “upper side,” “upper layer side,” or “outer side,” or simply “upper” or “outer,” and a side closer to the first support plate 100 is also referred to as a “lower side,” “lower layer side,” or “inner side,” or simply “lower” or “inner.”
Next, as illustrated in
The conductor layer 12 formed on the metal foil 11 is formed to have patterns including multiple conductor pads (P1) as illustrated. After the formation of the conductor layer 12, the plating resist is removed and the insulating layer 13 is coated on the conductor layer 12 and on the metal foil 11 exposed from the conductor patterns of the conductor layer 12. The insulating layer 13 can be formed, for example, by thermocompression bonding a film-like epoxy resin or the like onto the conductor layer 12 and the exposed portions of metal foil 11. The state illustrated in
By forming the conductor layer 12 and the insulating layer 13 on the metal foil 11 as illustrated, a first surface (1F) on one side of the wiring substrate to be manufactured is formed. All the multiple conductor pads (P1) included in the conductor layer 12 that forms the first surface (1F) are short-circuited by the metal foil 11.
Next, as illustrated in
Specifically, the electrolytic plating film can be formed using a so-called pattern plating method or the like using a plating resist that has predetermined openings at formation regions of the conductor patterns the conductor layer 12 and at positions of the conduction holes (14a). After the formation of the electrolytic plating film described above, the resist is removed. Then, a portion of the metal layer (seed layer) that is exposed by the removal of the plating resist and is not covered by the electrolytic plating film is removed by etching. As a result, the via conductors 14 and the conductor layer 12, each having a two-layer structure, can be integrally formed by the metal layer and the electrolytic plating film in the conduction holes (14a) and on the insulating layer 13. In the illustration, the metal layer and electrolytic plating film that form the via conductors 14 and the conductor layer 12 are simplified and are each illustrated as a single layer.
The lamination of the insulating layer 13 and the formation of the via conductors 14 and the conductor layer 12 are repeated according to the number of the insulating layers 13 and the number of the conductor layers 12 included in the wiring substrate to be manufactured. In the illustrated example, the wiring substrate 1 to be manufactured includes two insulating layers 13 and three conductor layers 12. However, the number of the insulating layers and the number of the conductor layers included in the wiring substrate to be manufactured are not limited to those illustrated in the drawing. The number of times of the process for laminating the insulating layers 13 and the conductor layers 12 can be increased or decreased as appropriate.
The wiring substrate 1 is formed such that the conductor layer 12 that forms an uppermost surface of the wiring substrate 1 (a surface on an opposite side with respect to the first surface (1F) facing the metal foil 11) includes multiple conductor pads (P2). The surface of the wiring substrate 1 that includes the multiple conductor pads (P2) is referred to as a second surface (1S). In the wiring substrate 1 in the illustrated example, two of the multiple (six) second conductor pads (P2) near a center are formed to be electrically connected to different first conductor pads (P1) via different conductor paths formed by the conductor layers 12 and the via conductors 14.
A material of the conductor layers 12 and the via conductors 14 of the wiring substrate 1 is not particularly limited as long as the material has a good conductivity and facilitates easy formation by plating. Examples of the material of the conductor layers 12 and the via conductors 14 include copper and nickel, and copper is preferably used. A material of the insulating layers 13 is not particularly limited as long as the material has a good insulating property. In addition to an epoxy resin described above, a bismaleimide triazine resin (BT resin), a phenol resin and the like may be used. The resin material forming the insulating layers 13 may contain a reinforcing material (core material) such as a glass fiber and/or inorganic filler such as silica.
On the second surface (1S) of the wiring substrate 1, as illustrated, a solder resist layer 15 having openings (15a) on the second conductor pads (P2) is formed. The solder resist layer 15 is formed on the upper surface of the insulating layer 13 exposed without being covered by the conductor layer 12 of the second surface (1S) of the wiring substrate 1, and on outer edges of the conductor pads (P2). For example, a layer formed of a photosensitive epoxy resin is formed on the conductor layer 12 and on the insulating layer 13 by printing or spray coating or the like, and the openings (15a) are formed by photolithography. The state of
Subsequently, in the state illustrated in
An inspection device commonly referred to as an open-short checker may be used for a conduction inspection. The open-short checker has multiple contact terminals and can measure a conduction resistance value of a conductor circuit connected via a pair of contact terminals among the multiple contact terminals. By comparing a detected conduction resistance value with a predetermined resistance value, presence or absence of an open defect or a short-circuit defect can be inspected. Each of the multiple contact terminals (en) of the inspection device is in contact with an exposed surface of a second conductor pad (P2), and a resistance value between any conductor pads (P2) is measured.
By inspecting whether or not a resistance value between conductor pads (P2) to be measured is within a predetermined range, presence or absence of a defect in a conductor circuit between the conductor pads (P2) can be determined.
In the state illustrated in
In particular, specifically, of the multiple (six) second conductor pads (P2) illustrated, the two near the center are respectively connected to different first conductor pads (P1) by different conductor paths. When a conductor circuit connecting these two second conductor pads (P2) near the center and the first conductor pads (P1) is open, such as when the conductor circuit is disconnected, a resistance value between the second conductor pads (P2) shows a very large value compared to that when the conductor circuit is not open. Therefore, it is possible to inspect an open defect in a conductor circuit (open inspection) based on a resistance value obtained by a measurement. In this way, in the method for manufacturing the wiring substrate of the present embodiment, an open inspection is possible even in a conductor circuit connecting the second conductor pads (P2) and the first conductor pads (P1), for which an open inspection cannot be performed when short-circuited by the metal foil 11.
A conduction inspection between the multiple second conductor pads (P2) performed in the state illustrated in
For a wiring substrate that has been determined as a non-defective product by the first conduction inspection, the following subsequent process is further performed. As illustrated in
For the second support plate 200, for example, a glass epoxy plate or the like formed by impregnating a reinforcing material such as a glass fiber with an epoxy resin is used. However, in addition to this, any material having an appropriate rigidity may be used. A plate-like body formed of glass, metal, or ceramics may be used. The adhesive layer 21 having appropriate adhesiveness (adhesion) with respect to the solder resist layer 15 is provided between the second support plate 200 and the solder resist layer 15, and the support plate 200 and the solder resist layer 15 are bonded together by the adhesiveness of the adhesive layer 21.
A material that forms the adhesive layer 21 is not particularly limited as long as the material can tightly adhere to the support plate 200 and the solder resist layer 15. At least, a material that can exhibit a stronger adhesive force with respect to the support plate 200 than with respect to the solder resist layer 15 is preferable as the material of the adhesive layer 21. The material that forms the adhesive layer 21 may be a material that loses adhesiveness with respect to the solder resist layer 15 due to a specific treatment such as ultraviolet irradiation or heating. For example, an acrylic resin may be used as the material of the adhesive layer 21.
Next, as illustrated in
In separating the metal foil layer (11b) and the carrier metal foil layer (11a) from each other, for example, the thermoplastic adhesive bonding the metal foil layer (11b) and the carrier metal foil layer (11a) is softened by heating, and, in this state, the metal foil layer (11b) and the carrier metal foil layer (11a) are pulled apart from each other. When the metal foil layer (11b) and the carrier metal foil layer (11a) are adhered to each other only in an outer peripheral portion, the metal foil layer (11b) and the carrier metal foil layer (11a) may be cut on an inner peripheral side of the adhering portion so that the adhering portion is removed. It is also possible to separate the metal foil layer (11b) and the carrier metal foil layer (11a) from each other by simply pulling the first support plate 100 and the second support plate 200 in mutually opposite directions. As illustrated in
Next, the metal foil layer (11b) exposed by being separated from the carrier metal foil layer (11a) is removed by etching. As illustrated in
Next, as illustrated in
When an external electronic component is mounted on the wiring substrate 1, in
Subsequently, in the state illustrated in
In the second conduction inspection, presence or absence of an open defect or a short-circuit defect can be inspected by measuring a conduction resistance value between the multiple first conductor pads (P1) that form the first surface (1F). The contact terminals (en) of the inspection device are connected to exposed surfaces of the multiple first conductor pads (P1), and, for example, a resistance value between any pair of first conductor pads (P1) is measured. When a measured resistance value is not within a predetermined range, it can be determined that there is a defect.
By separating the first support plate 100 and removing the metal foil layer (11b) illustrated in
Specifically, for example, contact terminals (en) are respectively connected to a pair of first conductor pads (P1) that are to be electrically separated from each other, and a resistance value between the pair of first conductor pads (P1) is measured. When there is a short circuit between the pair of first conductor pads (P1), the resistance value between the corresponding contact terminals (en) shows a very low value. As a result, a short-circuit defect between the first conductor pads (P1) that are to be completely electrically separated from each other can be detected.
The second conduction inspection between the multiple first conductor pads (P1) in the state illustrated in
In the manufacturing method described using the manufacture of the wiring substrate 1 as an example, in the second conduction inspection, a short-circuit inspection between the first conductor pads (P1) that are to be electrically separated from each other can be performed. Further, in the first conduction inspection, an open inspection between the second conductor pads (P2) that are connected to different first conductor pads (P1) via mutually different conductor paths can be performed. In particular, for the conductor paths for which an open inspection is not possible in the second conduction inspection illustrated in
A wiring substrate manufactured using the manufacturing method of the embodiment is not limited to a wiring substrate having the structure of the illustrated wiring substrate 1, and a wiring substrate having the structure, shape, and material exemplified in the present specification. On each the exposed surfaces of the conductor pads (the first and second conductor pads) of the wiring substrate, for example, multiple metal plating films or a single metal plating film such as Ni/Au, Ni/Pd/Au, or Sn, and a protective film, which may be an OSP film, may be formed. The wiring substrate 1 can have any number of conductor layers and any number of insulating layers. A conductor pattern of each of the conductor layers can be formed in any pattern.
A method of manufacturing a wiring substrate according to an embodiment of the present invention is not limited to the method described with reference to
Japanese Patent Application Laid-Open Publication No. 2017-11092 describes a conduction inspection method for a printed wiring board having a buildup layer. The build-up layer has multiple mounting pads on a surface on one side thereof, and a resin layer is provided on a surface on the other side of the build-up layer. Wirings in the buildup layer that are respectively electrically connected to the multiple mounting pads are electrically connected via internal conductor members penetrating the resin layer and a copper foil provided on a surface of the resin layer. A short-circuit defect of the wirings in the build-up layer is determined by measuring a resistance value between the multiple mounting pads.
In the conduction inspection method of the printed wiring board of Japanese Patent Application Laid-Open Publication No. 2017-11092, the conduction inspection is performed between the multiple mounting pads formed on the surface on one side of the buildup layer, and no conduction inspection is performed between conductor layers (conductor pads) on the surface on the other side. It is thought that detection of a conduction defect in the wirings in the buildup layer may be insufficient.
A method for manufacturing a wiring substrate according to an embodiment of the present invention includes: preparing a first support plate in which a metal foil is provided on a surface of a support substrate; forming, on the metal foil, a wiring substrate that has a first surface and a second surface on an opposite side with respect to the first surface, the first surface facing the metal foil; attaching a second support plate to the second surface of the wiring substrate; and, after the attaching of the second support plate, exposing the first surface by separating the support substrate from the metal foil and removing the metal foil from the first surface. The first surface includes multiple first conductor pads. The second surface includes multiple second conductor pads. Before the attaching of the second support plate to the second surface, a first conduction inspection between the multiple second conductor pads is performed. After the removing of the metal foil from the first surface, a second conduction inspection between the first conductor pads is performed.
According to an embodiment of the present invention, the inspection is performed between the multiple second conductor pads provided on the surface (the second surface) on one side of the wiring substrate and between the multiple first conductor pads provided on the surface (the first surface) on the other side of the wiring substrate. Inspection of presence or absence of a defect in the wiring substrate is more reliably performed.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-029881 | Feb 2022 | JP | national |
