Claims
- 1. A method for producing a microelectronic component having a sandwich construction, which comprises:providing a first substrate having a first conductor track plane; providing a plurality of semiconductor chips having first contact faces electrically connected to the first conductor track plane, and second contact faces opposite the first sides; providing a second substrate having a second conductor track plane with contact points; securing electrically conductive balls to the contact points of the second conductor track plane using an electrically conductive, flexible adhesive; applying an electrically conductive, flexible adhesive to the second contact faces of the plurality of semiconductor chips; and joining the first substrate and the second substrate together.
Priority Claims (1)
Number |
Date |
Country |
Kind |
196 40 445 |
Sep 1996 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
This is a division of U.S. application Ser. No. 09/282,092, filed Mar. 30, 1999 now U.S. Pat. No. 6,324,072 which was a continuation of copending international application PCT/DE97/02169, filed Sep. 24, 1997, which designated the United States.
US Referenced Citations (22)
Foreign Referenced Citations (2)
Number |
Date |
Country |
34 06 528 |
Aug 1985 |
DE |
WO9601498 |
Jan 1996 |
WO |
Non-Patent Literature Citations (2)
Entry |
“On the way to large scale integration” (Hascher), Electronics 26, 1995, pp. 50-54. |
Patent Abstracts of Japan No. 58-140143 A (Iwamatsu), dated Aug. 19, 1983. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE97/02169 |
Sep 1997 |
US |
Child |
09/282092 |
|
US |