The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
a-1d schematically illustrate cross-sectional views of a semiconductor device during the formation of contact plugs according to conventional process strategies, thereby resulting in metal-filled surface irregularities;
a-2d schematically illustrate cross-sectional views of a semiconductor device during various manufacturing stages for forming a contact plug by using a capping layer after a CMP process according to illustrative embodiments of the present invention;
a-3c schematically illustrate cross-sectional views of a semiconductor device during the formation of a planar interlayer dielectric material with a reduced number of surface irregularities according to still further illustrative embodiments of the present invention; and
a-4b schematically illustrate cross-sectional views of a semiconductor device during the formation of a planar interlayer dielectric with a reduced number of surface irregularities according to still further illustrative embodiments of the present invention.
Number | Date | Country | Kind |
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10 2006 015 096.1 | Mar 2006 | DE | national |