BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description of a preferred embodiment thereof taken in conjunction with the following drawings:
FIG. 1 illustrates a cross-sectional view of a portion of a partially completed semiconductor device in accordance with one embodiment.
FIG. 2 illustrates the semiconductor device of FIG. 1 after the formation of a pre-metal dielectric layer.
FIG. 3 illustrates the semiconductor device of FIG. 2 during an anneal process.
FIG. 4 illustrates the semiconductor device of FIG. 3 after the anneal process is complete.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Generally, the present invention provides a method for making a semiconductor device. The method includes forming a dielectric layer over a semiconductor layer. A radiation is applied to the dielectric layer for a duration not exceeding 10 milliseconds to cause a change in the stress of the dielectric layer. The application of the radiation may also activate source and drain regions of a transistor formed in the device. Applying the radiation for a short duration not exceeding 10 milliseconds provides the needed performance gains without adding significantly to the thermal budget for making the device. In addition, the stress is added using the same process step used to activate the source and drain. In one embodiment the radiation is applied using a laser.
FIG. 1 illustrates a cross-sectional view of a portion of a partially completed semiconductor device 10 in accordance with one embodiment. In one embodiment, semiconductor device 10 includes an N-channel transistor formed on an SOI (silicon-on-insulator) substrate 12. In another embodiment, substrate 12 may be bulk silicon. Generally the N-channel transistor is a conventional N-channel transistor and is representative of many N-channel transistors formed on device 10. Device 10 may also include P-channel transistors (not shown). Device 10 includes a semiconductor layer 14. Semiconductor layer 14 may be isolated using trench isolation such as for example shallow trench isolation (STI) structures 16 and 18. Source region 26 and drain region 28 are formed in the semiconductor layer 14 and are doped using p-type dopants. A gate dielectric layer is formed over the semiconductor layer 14 and a gate electrode layer is formed over the dielectric layer. Both the gate dielectric layer 20 and the gate electrode layer 22 are patterned as illustrated in FIG. 1 to form a patterned gate dielectric 22 and gate electrode 22 between the source region 26 and the drain region 28. The gate dielectric layer 20 may be formed using any suitable insulating material, such as for example, an oxide or a high-k dielectric. The gate electrode layer 22 may be formed using any suitable conductive material, such as for example, a metal, a conductive metal oxide, or polysilicon. Side wall spacers 24 are formed on the sides of the gate electrode and generally comprise nitride. Source and drain regions 30 and 32 are for other transistors not illustrated in FIG. 1. The other transistors may be, for example, P-channel transistors.
FIG. 2 illustrates semiconductor device 10 of FIG. 1 after the formation of a pre-metal dielectric layer 34. The pre-metal dielectric layer 34 is a plasma enhanced chemical vapor deposition (PECVD) dielectric layer comprising SiXNYHZ using a combination of growth chemicals or precursors comprising one or more of SiH4, NH3, N2, TMS (TriMethylSilane), He, Ar, or H2. Preferably, dielectric layer 34 comprises at least 30 atomic percent Hydrogen. The pre-metal layer is typically deposited at between 300-550 degrees Celsius at a sub-atmospheric pressure. The pre-metal layer is deposited to a thickness that will result in a thickness of about 300-1200 angstroms after radiation anneal (described below).
FIG. 3 illustrates semiconductor device 10 during a radiation anneal process. After deposition of the pre-metal dielectric layer 34, the semiconductor device 10 is radiated with a radiation 36 using a laser tool. A wafer having the device 10 is placed in the tool on a chuck that is pre-heated to between about 350-500 degrees Celsius, and preferably 400-425 degrees Celsius. The tool then causes the wafer to be scanned and locally exposes substantially the entire surface of the device using a predetermined scan pattern. In a preferred embodiment, the surface is exposed for about 1 millisecond to locally heat the device to about 900 to 1400 degrees Celsius. In other embodiments, the length of time device 10 is radiated is dependent on, for example, the power of the laser, the laser beam width, and the desired temperature. Also, the device 10 is radiated in an ambient atmosphere, or a controlled atmosphere containing one or more of air, Ar, He, N2, or the like. In addition, the device can be radiated with an absorber layer (not shown). The absorber layer can be used to reduce pattern density and material absorption effects in the device. The laser tool used in the radiation anneal process is an Ultratech LSA-100 available through Ultratech, Inc. In another embodiment, device 10 may be heated using a commonly available flash lamp tool that subjects the device to sufficient heat in a relatively short period of time. Heating the surface of device 10 causes pre-metal dielectric layer 34 to shrink and apply stress to substrate 12 as illustrated in FIG. 4. In addition, the application of radiation 36 activates source and drain regions 26 and 28, respectively. Note that the source and drain regions 30 and 32 of P-channel devices (not shown) are also activated at the same time. Because of the relatively short duration of radiation 36, diffusion of the dopants used to create source region 26 and drain region 28 is limited to less than about 20 angstroms.
FIG. 4 illustrates the semiconductor device of FIG. 3 after the radiation anneal process is complete to produce an annealed pre-metal dielectric layer 38 having tensile stress. Annealed pre-metal dielectric layer 38 produces a strain in the substrate 12. The strain increases carrier mobility, thus allowing an increased drain-to-source current in the N-channel transistor of device 10 over an unstrained device.
Because the annealed pre-metal dielectric layer 38 has tensile stress, it may not enhance carrier mobility for P-channel transistors, therefore in some embodiments the pre-metal dielectric layer 38 may be removed from over the P-channel devices (not shown).
Also, heating the substrate 12 for a relatively short period of time reduces a likelihood of cracks or fractures from forming in the annealed pre-metal dielectric layer 38. In addition, the strain is applied using the same process step that activates the dopants in the source and drain regions. Further, applying the radiation for a short duration not exceeding 10 milliseconds provides the mobility performance gain without adding significantly to the thermal budget for making the device.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. The terms a or an, as used herein, are defined as one or more than one. The terms including and/or having, as used herein, are defined as comprising (i.e., open language). As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Patent Application
20070298623
