NN9111377 (Reconfigurable Signature Generator. IBM Tech. Disclosure Bulletin, vol. #34 Issue #6, pp. 377-380, Nov. 1, 1991).* |
NN85123128 (Index Method for Test Pattern Reduction;IBM Tech. Disclosure Bulletin, vol. #28 Issue #7, pp. #3128-3129, Dec. 1, 1985).* |
NN86102004 (Self-Test N-Stream Online Isolation; IBM Tech. Disclosure Bulletin, vol. #: 29 Issue #5 pp. #:2004-2008; Oct. 1, 1986).* |
NN8912479 (Low-Cost Signature Analyzer and an Application; IBM Tech. Disclosure Bulletin; vol. #32 Issue #7 pp. #479-488; Dec. 1, 1989).* |
NB900818 (Pseudo-Random Pattern Self-Test of Arrays; IBM Tech. Disclosure Bulletin; vol. #33 Issue #3B pp. #18-19; Aug. 1, 1990).* |
NN931119 (Boundary Walking Sequences for Circuit Board Interconnect Test; IBM Technical Disclosure Bulletin; vol. #36, pp:19-22; Nov. 1, 1993 ).* |
NN83102637 (DIAGNOSIS Based on Signature Testing; IBM Technical Disclosure Bulletin; vol. #26, pp.:2637-2643; Octob 1983).* |
Transactions of Institute of Electronics D-1 vol. J80-D-1 No. 2, Feb. 1997. |
“An Analytical Approach to the Partial Scan Problem”, by Kunzmann et al., Journal of Electronic Testing (May 1990). |
“Pascant: A Partial Scan and Test Generation System”, by Bhawmik et al., IEEE (1991). |
“Partial Scan Designs Without using a Separate Scan Clock”, by Cheng, IEEE (1995). |
“Scan Design Oriented Test Technique for VLSI's, Using ATE”, by Oyama et al., IEEE (1996). |
“A Methodology for Programmable Logic Migration to ASIC's Including Automatic Scan Chain Insertion and ATPG”, by O'Connor, IEEE (1991). |
“An Analytical Approach to the Partial Scan Problem”, by Kunzmann et al., Journal of Electronic Testing, vol. 1, No. 2 (May 1990), pp. 163-174. |
“Test Compaction for Sequential Circuits”, by Niermann et al., IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 11, No. 2 (Feb. 1992), pp. 260-267. |
“A Partial Scan Design Method Based on n-Fold Line-up Structures”, by Hosokawa et al., Proceedings Sixth Asian Test Symposium (ATS '97), Nov. 1997, p. 306-311. |
“An Exact Algorithm for Selecting Partial Scan Flip-Flops”, by Chakradhar et al., Proceedings of 31st ACM/IEEE Design Automation Conference (1994), pp. 81-86. |
“Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques”, by Pomeranz et al., Proceedings of FTCS-26 (1996), pp. 53-61. |
“Compaction of ATPG-Generated Test Sequences for Sequential Circuits”, by Roy et al., Proceedings of 1988 IEEE (1988), pp. 382-385. |
“Design for Testability”, Publication by Computer Science Press (1990), Chapter 9, pp. 343-395. |