Method of fabricating a BCCD channel with stair-case doping by self-alignment

Abstract

This invention relates to a method of forming a charge coupled device (CCD) channel which has a trench-type multi-potential profile. To form the multi-potential profile, ion implantation is performed several times with a self-alignment mask using a polysilicon layer. This method simplifies the fabrication process and prevents charges from diffusing over the entire CCD channel laterally when the amount of charge is small. This results in charge confinement in a trench in the middle of the channel, enhancing self-induced field and fringing field. Consequently, charge transfer efficiency is improved for small amount of charge.

Description

BACKGROUND OF INVENTION

1. Field of the Invention

This invention relates to a fabricating method for charge coupled device (CCD) channel by self-alignment, particularly to the method for fabricating the CCD channel which an enhancement of charge transfer efficiency can be obtained in case that small amount of charge exist in a CCD channel.

2. Description of Related Art

FIGS. 1A-1C show the configuration of a conventional CCD channel. As shown in these figures, the CCD channel consists of first polysilicon gates(2 and 2a) and second polysilicon gates(5 and 5a) which are placed alternatively. With this scheme, two-phase clock is necessary for the charge transfer.

However, conventional CCD channel structures have a critical shortcoming which is a poor charge transfer efficiency when a small amount of charge exists in the channel. This is because conventional CCD channels are laterally too wide for small amount charge which diffuse over the channel as shown in FIG. 1C, reducing self-induced field and fringing field. Consequently, charge transfer efficiency becomes degraded.

OBJECT OF INVENTION

The object of this invention is to provide a fabricating method which overcomes the shortcoming of the conventional art described above.

SUMMARY OF INVENTION

To prevent small amount of charge from diffusing over the channel, a trench-type potential is formed in the middle of the channel only under second polysilicon gates 5 as shown in FIGS. 2A and B. Then, the charges become confined in small volume, consequently, efficient charge transfer is possible.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS 1A-1C show the configurations of a conventional CCD channel;

FIG. 1A is a top-view;

FIG. 1B is a configuration and a potential profile in the direction of A--A in FIG. 1A;

FIG. 1C is a cross sectional view in the direction of B--B in FIG. 1A;

FIG. 2A-2B show the configurations of the present invention;

FIG. 2A is a configuration and a potential profile in the direcion of A--A in FIG. 1A;

FIG. 2B is a cross sectionasl view in the direction of B--B in FIG. 1A; and

FIGS. 3A-3E show a procedure of fabricating process of a CCD channel by self-alignment according to the present invention.

DETAILED DESCRIPTION OF THIS INVENTION

FIGS. 3A-3E show a procedure of the fabricating process for the device structure whose potential profile looks like FIG. 2B. Detailed description of the procedure is as follows.

Firstly, ion implantation is performed over the entire active areas 1 as shown in FIG. 3A. Then, polysilicon is deposited and etched out partially to have first polysilicon gate 2 of FIG. 3B. Nextly, photoresist (PR) process is performed, i.e., PR is deposited and developed to have the opening 3 in FIG. 3C. Then, second ion implantation (I/I) is performed. In this case, first polysilicon gate 2 plays a role of a mask for the I/I. Thus, self-alignment is accomplished. Another PR process is followed to have the opening 4 in FIG. 3D, and the third I/I is performed. Also in this case, first polysilicon gate 2 is used as a self-alignment mask for I/I. If we need more steps in the potential profile, PR process and I/I process can be repeated. Finally, polysilicon is deposited and etched out to have second polysilicon gate 5 as shown in FIG. 3E.

Performing above procedure, a trench-type multi-potential profile can be obtained as shown in FIG. 2B and small amount of charge can be confined in the trench which is a lower potential level. Therefore, charges confined in the area of second polysilicon gate 5 in FIG. 3E result in enhancements of self-induced field and fringing field which are beneficial to the charge transfer in a CCD channel.

Aforementioned scheme will be very useful in an application of high-fidelity and high-resolution camcorder, where efficient charge transfer is necessasry.

Claims

1. A fabricating method for a CCD channel by self-alignment comprising the following steps of:

performing ion implantation in a selected active area of a semiconductor substrate;

depositing a first polysilicon layer on said active area;

etching out a selected area of said first polysilicon layer to create a first polysilicon gate;

depositing a layer of PR having an opening overlying a portion of said first polysilicon gate;

performing a second ion implantation using said first polysilicon gate as a mask to provide self-alignment;

forming another PR layer having an opening larger than and overlying said first opening;

performing a third ion implantation using said first polysilicon gate as a mask to provide self-alignment;

depositing a second layer of polysilicon atop said selected active area; and

etching out a selected area of said second layer of polysilicon to provide a second polysilicon gate over a portion of said active area adjacent to said first polysilicon gate.

2. A method according to claim 1, wherein the impurity concentration of said selected active area not beneath either of said first or second silicon gates is lower than that of the active area beneath said first polysilicon gate and that of the selected active area beneath said first polysilicon gate is lower than said portion of said active area beneath said second polysilicon gate.

3. A method according to claim 1, wherein the resulting potential profile has the shape of a staircase in the longitudinal direction along the channel which includes a multi-potential profile under said second polysilicon gate.

4. A method according to claim 3, wherein additional PR process and ion implantation are included to create additional steps in said multi-potential profile.

5. A method according to claim 1, wherein a trench-type, multi-potential doping profile is formed in the middle of the region under said second polysilicon gate.