Method of fabricating semiconductor device and polishing apparatus used therefor

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method of fabricating a semiconductor device, which method is suitable for use in fabrication of a semiconductor device of a type in which an interconnection layer is formed by a Damascene process, and to a polishing apparatus used for the fabrication method.

[0002] The recent development of VLSIs (Very Large Scale Integrated Circuits) toward higher density and higher integration degree is supported by a lithography technique capable of keeping up with very fine regions of the order of sub-micron or less. Such a lithography technique, however, has an inconvenience that since irregularities on a surface of a silicon wafer are amplified along with progress of a device fabricating process, a resolution and a focal depth cannot be made compatible with each other in a projection exposure process, with a result that it is difficult to gain a proper focus on both a recess and a projection of the irregularities on the wafer surface. To cope with such an inconvenience, it is essential to perform, in a suitable step of the fabrication process, a planarization treatment for removing the irregularities of the wafer surface in order to reduce each of stepped portions of the irregularities to a focal depth or less.

[0003] One of techniques of planarizing a wafer surface is a CMP (Chemical Mechanical Polishing) method. As is well known, according to the CMP method, a surface to be polished of a wafer is polished with a polishing cloth via slurry, to be planarized by combination of a chemical action to oxidize the wafer surface with the slurry and a mechanical action to polish the wafer surface with the polishing cloth.

[0004] The CMP method has been used for planarizing an interlayer insulating film to be ready for forming an interconnection pattern on each of second and later layers. In recent years, however, such a CMP method has come to be applied to a so-called Damascene process of burying an interconnection metal film in holes or grooves formed in an insulating film. To be more specific, the Damascene process involves forming contact holes for connecting an upper interconnection layer to a lower interconnection layer and/or interconnection grooves in an insulating film, forming an interconnection metal film thereon, and removing the metal film excluding portions thereof in the contact holes and/or the grooves by the CMP method. The Damascene process is also called “buried interconnection forming process”. In the Damascene process, since an insulating film has been already planarized at the time when an interconnection pattern is formed in a state being buried in the insulating film, it is possible to omit the step of planarizing the insulating film.

[0005] An interconnection metal film used for the Damascene process is made from tungsten (W), aluminum (Al) or copper (Cu). In particular, the use of Cu as a material for an interconnection metal layer is advantageous in terms of reduction in resistance of the interconnection metal layer and improvement of electromigration resistance of the interconnection metal layer.

[0006] In the CMP method applied to the Damascene process, an insulating film with its polishing rate lower than that of an interconnection metal layer buried in the insulating film becomes a polishing stopper. The polishing degree of the polishing layer, however, differs between different regions, that is, different interconnection pattern portions of the interconnection layer. Specifically, the polishing degree of the interconnection layer differs between a high density interconnection pattern portion and a low density interconnection pattern portion, or between a large-sized interconnection pattern portion and a small-sized interconnection pattern portion. Accordingly, although an insulating film functions somewhat as a polishing stopper, it cannot prevent a high density interconnection pattern portion from being over-polished, with a result that a thickness of the interconnection layer at the high density interconnection pattern portion is reduced. This phenomenon is called “thinning”. On the other hand, at a wider interconnection portion in a relatively low density interconnection pattern portion, a central portion of the interconnection portion is recessed. This phenomenon is called “dishing”. The dished portions occurring in the interconnection layer reduce the reliability of the interconnection layer and also cause irregularities of a surface of an insulating film formed thereon. The dishing occurs due to a difference in polishing rate between an interlayer insulating film and an interconnection metal layer buried in the interlayer insulating film when the interconnection metal layer is over-polished. If a polished amount of an interconnection metal layer, for example, Cu layer is reduced in order to avoid over-polishing, Cu remains between the adjacent interconnection portions. This phenomenon is called “metal residue”. The metal residue results in an interconnection failure.

[0007] Accordingly, in the case of carrying out the CMP method, it is required to highly accurately control a polished amount, and it is important to prevent over-polishing of each interconnection portion of an interconnection layer by suitably deciding a polishing end point.

[0008] To accurately control a polished amount for preventing over-polishing, optical measurement methods characterized by a high spatial resolution have been often adopted. For example, Japanese Patent Laid-open No. Hei 11-307604 discloses a technique of identifying the presence of a metal residue on an insulating film on the basis of laser light reflected from the insulating film; and Japanese Patent Laid-open No. Hei 9-298174, Hei 9298175, and Hei 9-298176 disclose a technique of measuring a thickness distribution of an insulating film while rotating a wafer by a spectral reflectance measurement method.

[0009] The former method, however, only detects the presence or absence of a metal film on an insulating film, and is not configured to detect over-polishing such as dishing of an interconnection portion. The latter method is intended to detect a surface shape in the same radius region within a wafer surface in average, and is therefore difficult to highly accurately evaluate polishing of an interconnection layer. With respect to an interconnection layer formed by the damascene process, as described above, there occur both a problem associated with dishing occurring in a coarse interconnection portion and a problem associated with a separation width between adjacent two of interconnection portions in a dense interconnection pattern portion. In this regard, it is very difficult for the above-described methods to highly accurately detect a polishing end point of a device provided with an interconnection layer having dense and coarse interconnection pattern portions.

[0010] By the way, before product wafers are polished by the CMP apparatus, it is usually decided whether or not the CMP apparatus is in a state capable of polishing the product wafers or decided under which conditions the wafers should be polished, by a manner of polishing a pilot wafer (monitor wafer) and evaluating a polishing state thereof. In the present CMP technique, however, since a variation in processing characteristic is larger than a variation in processing characteristic of any other semiconductor fabricating apparatus, it is required to frequently supply monitor wafers for highly accurately polishing wafers. On the other hand, there is known a technique in which an inspection (evaluation) unit is provided in the vicinity of a loader/unloader of the CMP apparatus in order to evaluate a polished wafer as a product; however, in this technique, since the evaluation of a wafer as a product is performed immediately before unloading of the wafer, there occurs a problem that it is difficult to feed back information such as a change in polishing condition to the CMP apparatus.

[0011] Each of the above-described documents, that is, Japanese Patent Laid-open No. Hei 9-298174, Hei 9-298175, Hei 9-298176, and Hei 11-307604 discloses a technique of providing an inspection step for evaluating polishing of a wafer during polishing of the wafer, wherein if the surface state of the wafer is within a specific surface condition, the polishing is stopped and if not so, the polishing is continued. With this technique, it is possible to reduce a time required for evaluating polishing of a monitor wafer and the consumption of the monitor wafer, to perform optimum polishing without effects of a variation in polishing rate and a variation in thickness of each product wafer, and to suppress a loss of product wafers due to occurrence of abnormality of the CMP apparatus.

[0012] Such a technique, however, has a problem that since a polishing work for product wafers cannot be performed during the inspection step, a loss time by inspection becomes larger, thereby failing to improve the throughput of the CMP apparatus.

SUMMARY OF THE INVENTION

[0013] An object of the present invention is to provide a method of fabricating a semiconductor device, which is capable of suitably polishing an interconnection metal film and improving a throughput of a polishing apparatus, and to provide a polishing apparatus used for the above fabrication method.

[0014] To achieve the above object, according to a first aspect of the present invention, there is provided a method of fabricating a semiconductor device, including: a wafer preparation step of preparing a wafer on which an interconnection metal film is formed on an insulating film provided with interconnection grooves; a polishing step of removing the interconnection metal film excluding portions thereof in the grooves by polishing, to form an interconnection layer composed of interconnection layer portions buried in the interconnection grooves; and an inspection step of inspecting a state of a plane to be polished of the wafer; wherein the inspection step further includes: a step of measuring an in-plane separation width between adjacent two of the interconnection layer portions; and a step of measuring a dishing amount of the interconnection layer portion.

[0015] With this configuration, since the inspection step includes the step of measuring an in-plane separation width between adjacent two of the interconnection layer portions, and the step of measuring a dishing amount of the interconnection layer portion, it is possible to detect a polished amount of a coarse interconnection pattern portion and a polished amount of a dense interconnection pattern portion, and hence to suitably set polishing conditions for polishing a device forming region having coarse and dense interconnection pattern portions and highly accurately control a polishing end point for the device forming region. In particular, it is possible to suitably evaluate a polishing state of an interconnection layer formed by the Damascene process in consideration of polished amounts of coarse and dense interconnection pattern portions, and hence to guarantee a high quality of the interconnection layer.

[0016] The inspection step is preferably performed in a specific chip region within a surface of the wafer.

[0017] With this configuration, since the evaluation of polishing can be performed on the basis of not an average value but an actually measured value, it is possible to enhance the accuracy of the evaluation of polishing and to detect a variation in polishing within a wafer surface.

[0018] The inspection step for the wafer is preferably performed during a period of time in which other wafers are polished in the polishing step.

[0019] With this configuration, since a plane to be polished of a wafer can be evaluated without stoppage of production of products, it is possible to improve the throughput of the polishing apparatus.

[0020] The metal film is preferably made from copper.

[0021] With this configuration, it is possible to suitably perform the Damascene process using a soft metal material and hence to reduce an electric resistance of the device and also improve the electromigration resistance of the device.

[0022] To achieve the above object, according to a second aspect of the present invention, there is provided a polishing apparatus including: a polishing unit having a plurality of polishing portions for polishing a layer to be polished formed on a surface of a wafer; transfer means for transferring the wafer between the polishing unit and the same; a relay unit, disposed between the polishing unit and the transfer unit, for temporarily supporting the wafer to be transferred; and a carrier for circulating the wafer to the polishing portions and the relay unit; wherein the relay unit is provided with inspection means for evaluating the plane to be polished of the polished wafer.

[0023] With this configuration, a wafer supplied from a loader/unloader unit to the relay unit by the transfer means is carried to each polishing portion in the polishing unit by the carrier, to be subjected to a specific polishing work, and the wafer having been polished by the polishing unit is supplied to the relay unit by the carrier and is transferred to the loader/unloader unit by the transfer means, wherein a plane to be polished of the polished wafer supplied to the relay unit is evaluated by the inspection means and it is decided whether or not the wafer has been suitably subjected to the polishing works, and if it is decided that the wafer has been not sufficiently polished, the wafer is returned again to the polishing unit while if it is decided that the wafer has been over-polished, the setting of the polishing conditions such as a polishing time is changed. Accordingly, since specific polishing works can be performed at the plurality of polishing portions during a period of time in which the already polished wafer is inspected, it is possible to improve the throughput of the polishing apparatus, and also to feed back an inspection result by the inspection means to the polishing portions and change, if abnormality is detected, the polishing conditions for the wafers during production. As a result, it is possible to ensure a suitable polishing end point.

[0024] The inspection means preferably includes: an inspection stage for supporting the wafer; and a measurement head, disposed opposite to the plane to be polished of the polished wafer, for optically detecting a state of the plane to be polished of the polished wafer.

[0025] With this configuration, it is possible to evaluate polishing with a high spatial resolution.

[0026] The measurement head is preferably movable in the direction parallel to the plane to be polished of the polished wafer.

[0027] With this configuration, it is possible to evaluate polishing of each chip within the wafer surface, and hence to highly accurately evaluate polishing of a plane to be polished of a wafer.

[0028] The polishing apparatus preferably further includes control means for changing the setting of polishing conditions at the polishing portions on the basis of an inspection result by the inspecting means.

[0029] With this configuration, since an evaluation result of a plane to be polished of an already polished wafer can be fed back to polishing of another wafer performed in parallel to the inspection of the already polished wafer, it is possible to keep suitable polishing conditions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030]
FIG. 1 is a plan view showing a schematic configuration of a polishing apparatus according to an embodiment of the present invention;

[0031]
FIG. 2 is a sectional side view showing one example of a configuration of each of polishing portions of the polishing apparatus shown in FIG. 1;

[0032]
FIG. 3 is a side view showing a configuration of a relay unit shown in FIG. 1;

[0033]
FIGS. 4A to 4D are typical sectional views illustrating sequential steps of a Damascene process applied to the embodiment of the present invention; wherein FIG. 4A shows an interconnection groove forming step, FIG. 4B shows a barrier metal layer forming step, FIG. 4C shows an interconnection metal film forming step, and FIG. 4D shows a CMP step;

[0034]
FIG. 5 is a detailed sectional view illustrating an in-plane separation width between adjacent two of buried interconnection layer portions formed by the Damascene process according to the embodiment of the present invention;

[0035]
FIG. 6 is a detailed sectional view illustrating a dishing amount of one of the buried interconnection layer portions formed by the Damascene process according to the embodiment of the present invention;

[0036]
FIG. 7 is a plan view of a wafer typically illustrating objects whose polished states are to be evaluated according to the embodiment of the present invention; and

[0037]
FIG. 8 is a flow diagram illustrating an operation of the polishing apparatus according to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

[0039]
FIG. 1 is a plan view showing a schematic configuration of a polishing apparatus according to an embodiment of the present invention. A polishing apparatus 1 according to this embodiment includes a polishing unit 3 having a plurality of polishing portions (first, second, and third polishing portions 2A, 2B and 2C are shown in the figure), a transfer robot 5 for transferring wafers between the polishing unit 3 and a loader/unloader unit 4, and a relay unit 6 for temporarily supporting wafers before transfer of the wafers from the transfer robot 5 to the polishing unit 3 or from the polishing unit 3 to the transfer robot 5.

[0040] The polishing portions 2A, 2B and 2C and the relay unit 6 are disposed on the same circumference, and four carriers (heads) 7, each of which is adapted to support a wafer W, are provided for the polishing portions 2A, 2B and 2C and the relay unit 6. Each carrier 7 is intermittently turned around a center O in the direction shown by an arrow (counterclockwise) in the figure, to circulate the wafer W from one to another of the polishing portions 2A, 2B and 2C and the relay unit 6 in this order. In this case, the intermittently circulating movement of one wafer W is synchronized with each of the intermittently circulating movements of the other wafers W.

[0041] The polishing apparatus 1 also includes a control unit 8 for controlling polishing conditions, such as a polishing time, a polishing pressure, and a supplied amount of slurry, of each of the polishing portions 2A, 2B and 2C, and also controlling operations of the transfer robot 5 and the carriers 7. It is to be noted that the control unit 8 is, as will be described later, configured to change the setting of the polishing conditions of each of the polishing portions 2A, 2B and 2C on the basis of an inspection result from an inspecting means provided on the relay unit 6.

[0042] Each of the polishing portions 2A, 2B and 2C has the same configuration, and is typically configured as a CMP (Chemical Mechanical Polishing) apparatus shown in FIG. 2. Each of the polishing portions 2A, 2B and 2C has a polishing plate (platen) 11 supported by a rotating shaft 9 rotatable in the direction shown by an arrow C. A polishing cloth 10 is laid on an upper surface of the polishing plate 11. The carrier 7 has a rotating shaft 12 rotatable in the direction shown by an arrow D. A back surface of the carrier 7 is configured to attractively hold the wafer W with its plane Wp to be polished directed downwardly. The plane Wp to be polished of the wafer W is polished with slurry (abrasive) 13 by rotating the rotating shafts 9 and 12 in the directions reversed to each other while pressing the wafer W to the polishing cloth 10.

[0043] According to this embodiment, an end point monitor (not shown) is provided for each of the polishing portions 2A, 2B and 2C, and each of the polishing portions 2A, 2B and 2C is controlled on the basis of an output from the monitor by the control unit 8. The end point monitor may be of a known type in which changes in state of the plane Wp to be polished of the wafer W are detected in average on the basis of light reflected from the plane Wp to be polished of the wafer W during polishing operation.

[0044] The relay unit 6 is provided with the above-described inspecting means according to the present invention. As shown in FIG. 3, the relay unit 6 includes an inspection stage 14 for supporting a peripheral edge of the plane Wp to be polished of the wafer W. The inspection stage 14 is formed into an approximately cylindrical shape having a hollow potion 14a. A measurement head 15 for optically detecting a surface state of the plane Wp to be polished is disposed under the inspection stage 14. The measurement head 15 is supported on a movable base 16 movable in parallel to the plane Wp to be polished.

[0045] The measurement head 15 emits light L of a short wavelength in an ultraviolet region to irradiate the plane Wp to be polished of the wafer W therewith and receives the light L reflected therefrom. The measurement head 15 supplies its output to the control unit 8. As will be described later, buried interconnection layer portions are formed on the plane Wp to be polished of the wafer W by the Damascene process. On the basis of the output from the measurement head 15, the control unit 8 measures an in-plane separation width between adjacent two of the buried interconnection layer portions and a dishing amount of a wider one of the interconnection layer portions. If the measured value of each of the in-plane separation width and the dishing amount is out of a specific range, then as will be described later, the wafer W is returned to the polishing portions 2A, 2B and 2C to be polished, or a signal indicating an abnormality of the polishing apparatus is issued.

[0046] A method of fabricating a semiconductor device using the polishing apparatus configured as described above will be described below. According to this embodiment, the polishing apparatus 1 is used in the step of forming (or burying) a copper interconnection layer in an insulating film by the Damascene process as shown in FIGS. 4A to 4D. The step of burying a copper interconnection layer in an insulating film by the Damascene process will be first described.

[0047] After grooves 22 in which interconnection layer portions are to be buried are formed in an insulating film 21 typically made from SiO2 (silicon dioxide) by a plasma etching process (FIG. 4A), a barrier metal layer 23 is formed on the insulating film 21 (FIG. 4B), and a metal layer 24 made from Cu is formed thereon by a CVD process or a plating process (FIG. 4C). The barrier metal layer 23 is formed for preventing diffusion of Cu to the insulating film 21 and improving adhesion of Cu to the insulating film 21. The barrier metal layer 23 is typically made from TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), or WN (tungsten nitride). Subsequently, the Cu layer 24 and the barrier metal layer 23 excluding portions thereof in the grooves 22 are removed by the CMP process, whereby a Cu interconnection layer is formed on the insulating film 21 in such a manner that Cu interconnection layer portions 24A of the Cu interconnection layer are buried in the grooves 22 (FIG. 4D).

[0048] The wafer W in the state shown in FIG. 4C (hereinafter, referred sometimes to as “unpolished wafer”) is carried to the loader/unloader unit 4 of the polishing apparatus 1, and is then polished into the state shown in FIG. 4D by the polishing portions 2A, 2B and 2C. The operation of the polishing apparatus 1 will be described below.

[0049]
FIG. 8 is a flow diagram illustrating the operation of the polishing apparatus 1 of this embodiment. The unpolished wafer W held by the loader/unloader unit 4 is transferred onto the inspection stage 14 of the relay unit 6 with the plane Wp to be polished directed downwardly by the transfer robot 5 (step S1) . After that, the wafer W is sequentially circulated to the polishing portions 2A, 2B and 2C in this order, to be subjected to specific polishing works (steps S2 and S3).

[0050] The carrier 7 positioned at the relay unit 6 is attractively holds the back surface of the wafer W, and is moved to the first polishing portion 2A. At the first polishing portion 2A, the plane Wp to be polished of the wafer W is subjected to a first polishing work, more specifically, rough polishing for removing irregularities on the surface of the Cu film 24. A polishing end point is determined by a thickness distribution of the Cu film 24 detected by the end point monitor.

[0051] The carrier 7 is moved from the first polishing portion 2A to the second polishing portion 2B. At the second polishing portion 2B, the plane Wp to be polished of the wafer W is subjected to a second polishing work, more specifically, Cu removal polishing for removing the Cu film 24 on the insulating film 21 excluding portions thereof buried in the grooves 22. A polishing end point is determined on the basis of an in-plane average change in intensity of reflected light, which change occurs due to a change of the wafer surface from the Cu film 24 to the barrier metal 23.

[0052] The carrier 7 is moved from the second polishing portion 2B to the third polishing portion 2C. At the third polishing portion 2C, the plane Wp to be polished of the wafer W is subjected to a third polishing work, more specifically, a bimetal removal polishing for removing the barrier metal layer 23 on the insulating film 21 excluding portions thereof buried in the grooves 22. A polishing end point is determined on the basis of an in-plane average change in intensity of reflected light, which change occurs due to a change of the wafer surface from the barrier metal layer 23 to the insulating film 21.

[0053] After the plane Wp to be polished of the wafer W is polished from the state shown in FIG. 4C to the state shown in FIG. 4D by the polishing portions 2A, 2B and 2C (step S4), the carrier 7 is moved again from the third polishing portion 2C to the relay unit 6. At the relay unit 6, the wafer W is placed on the inspection stage 14 as shown in FIG. 3 (step S5). The surface state of the plane Wp to be polished of the wafer W is inspected (step S6), and the polished wafer W placed on the inspection stage 14 is held by the transfer robot 5 and is transferred to the loader/unloader unit 4 (step S7). The inspection of the surface state of the plane Wp to be polished of the wafer w will be more fully described below.

[0054] After the wafer W is placed at a suitable position on the inspection stage 14 with the plane Wp to be polished directed downwardly, the measurement head 15 positioned under the inspection stage 14 is moved to a position facing to each of predetermined specific chip regions C1, C2, and C3 (see FIG. 7) on the wafer W, to inspect the surface state in each of the chip regions C1, C2, and C3.

[0055] According to this embodiment, an in-plane separation width X between the adjacent Cu interconnection layer portions 24A in a dense interconnection pattern in which the Cu interconnection layer portions 24A are densely arranged (see FIG. 5), and a dishing amount ΔY of one of the Cu interconnection layer portions 24A in a coarse interconnection pattern in which the Cu interconnection layer portions 24A are coarsely arranged (see FIG. 6) are measured by an intensity distribution and a deviation in phase of light L emitted to irradiate the wafer surface and reflected therefrom. In particular, since an opening 22a of the groove 22 is tapered, the separation width X corresponding to a polished amount can be detected, to measure a thinning amount of the interconnection layer and to indirectly measure a thickness of the insulating film 21.

[0056] Since the object to be measured differs depending on whether or not the interconnection pattern is a dense pattern or a coarse pattern, it is possible to detect whether or not a device forming region having dense and coarse interconnection patterns has been suitably polished, and to suitably control the polishing conditions in the case of polishing a soft metal interconnection layer, typically, a Cu layer by using the CMP. This makes it possible to ensure a high quality guarantee of an interconnection layer, that is, obtain an interconnection layer having a low resistance and a high electromigration resistance.

[0057] In this inspection step, the above-described measurement is performed at several chips in different radius regions on the wafer W, for example, the chip C1 positioned at a central portion of the wafer W, the chip C2 positioned at a peripheral portion of the wafer W, and the chip C3 positioned therebetween. With this measurement, it is possible to inspect whether or not the overall wafer W has been suitably polished.

[0058] According to this embodiment, the polishing conditions of the polishing portions 2A, 2B and 2C are set such that an in-plane separation width X between the interconnection layer portions 24A becomes about 0.2 μm and the dishing amount ΔY becomes 50 nm or less. If the separation width X is less than about 0.2 μm, since there is a possibility of occurrence of an interconnection short-circuit failure and/or a metal residue, it is decided that the wafer W has been not sufficiently polished (step S6). In this case, the wafer W is returned to the polishing portions 2A, 2B and 2C to be polished again. If the separation width X and the dishing amount ΔY are more than 0.2 μm and 50 nm, respectively, it is decided that the wafer W has been over-polished (step S6). In this case, the polishing conditions of the polishing portions 2A, 2B and 2C are changed and/or a signal indicating an abnormality of the polishing apparatus 1 is issued for performing maintenance of the polishing apparatus 1. A signal output timing of the end point monitor in each of the polishing portions 2A, 2B and 2C may be changed.

[0059] In the above-described operation of the polishing apparatus 1, as described above, the intermittently circulating movement of each carrier 7 is synchronized with each of the intermittently circulating movements of the other carriers 7. Accordingly, the wafers W are separately polished by the polishing portions 2A, 2B and 2C, and the wafer W immediately after being polished is subjected to the above-described inspection at the relay unit 6. As a result, the planes Wp to be polished of the wafers W can be polished without stoppage of production of the product wafers W. In particular, changes in polishing conditions based on an inspection result in the inspection step are fed back to the polishing step at the polishing portions 2A, 2B and 2C, which polishing step is carried out in parallel to the inspection step, to thereby keep suitable polishing works.

[0060] While the embodiment of the present invention has been described, the present invention is not limited thereto, and it is to be understood that various changes may be made without departing from the technical thought of the present invention.

[0061] For example, the configurations of the above-described embodiment may be changed as follows.

[0062] The interconnection metal layer 24, which is made from Cu in the embodiment, may be made from another metal material such as Al or W.

[0063] The wafer W is stepwise polished by the first, second and third polishing portions 2A, 2B and 2C in the embodiment. The present invention, however, is not limited thereto but may be configured such that each of the polishing portions 2A, 2B and 2C independently performs all polishing works of the wafer W. Further, the polishing portions 2A, 2B and 2C are not necessarily disposed on the same circumference, but may be linearly disposed in parallel to each other.

[0064] The configuration of the CMP apparatus is not limited to that described in the above embodiment. For example, the present invention is applicable to a CMP apparatus in which one wafer is polished by using a plurality of pressing heads.

[0065] A distribution of intensity of reflected light is used for measuring an in-plane separation width X between the interconnection layer portions 24; however, secondary electrons generated from a plane irradiated with an electron beam may be used therefor.

Method of fabricating semiconductor device and polishing apparatus used therefor

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