In the fabrication of semiconductor integrated circuit (IC) devices, various device features such as insulation layers, metallization layers, passivation layers, etc., are formed on a semiconductor substrate. It is known that the quality of an IC device fabricated is a function of the processes in which these features are formed. The yield of an IC fabrication process in turn is a function of the quality of the device fabricated and a function of the cleanliness of the manufacturing environment in which the IC device is processed.
The ever increasing trend of miniaturization of semiconductor IC devices requires more stringent control of the cleanliness in the fabrication process and the process chamber in which the process is conducted. In recent years, contamination caused by particles or films has been reduced by the improvements made in the quality of clean rooms and by the increasing utilization of automated equipment which are designed to minimize exposure to human operators. However, even though contaminants from external sources have been reduced, various contaminating particles and films are still generated inside the process chamber during the processing of semiconductor wafers. Therefore, attention has been drawn to an effective chamber cleaning method.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “over”, “overlying”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or step in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The present disclosure provides a novel method suitable for cleaning a process chamber. In some embodiments, the method of the present disclosure merely requires a single cleaning operation after multiple wafers are respectively deposited with process films in the chamber, and therefore, the chamber cleaning time can be significantly reduced because no chamber cleaning step is required between the deposition steps of two adjacent wafers.
More specifically, in some embodiments, the deposition step of a non-process film, instead of the conventional chamber cleaning step, is provided between the deposition steps of two adjacent wafers. In some embodiments, a process film indicates a functional film or a target film remained on a wafer, and a non-process film indicates a non-functional film or a season film not required for a wafer. When a process film is deposited on a wafer in a process chamber, the process film is also deposited on the interior surface of the process chamber. More specifically, a process film is deposited on the interior chamber surface when a wafer is processed in the chamber. On the contrary, a non-process film is deposited on the interior chamber surface when a wafer is not present in the chamber. In the process chamber, the non-process film is formed over the adjacent process film so as to adhere the process film to the interior surface and therefore prevent the films from contaminating a wafer that is being processed in the chamber. After multiple wafers are respectively deposited with process films in the chamber, the undesired process films and non-process films are removed from the interior surface of the process chamber by an extended cleaning operation.
Referring to
In some embodiments, the process chamber 10 includes a chamber housing 100 which contains a wafer support pedestal 150. A heater element 170 may be embedded in the wafer support pedestal 150 for heating a wafer supported on the wafer support pedestal 150. An AC power supply 106 is typically connected to the heater element 170. A temperature sensor 172 is typically embedded in the wafer support pedestal 150 to monitor the temperature of the pedestal 150. The measured temperature is used in a feedback loop to control the power supplied to the heater element 170 through the AC power supply 106.
In some embodiments, the process chamber 10 further includes a gas distribution plate or a showerhead 120 provided in the top of the chamber housing 100. The showerhead 120 is configured for the introduction of process gases into the chamber housing 100. A gas panel 130, which is used to select the gases to be introduced into the chamber 10 through the showerhead 120, is connected to the showerhead 120. A vacuum pump 102 is operably connected to the chamber housing 100 to maintain proper gas flow and pressure inside the chamber housing 100, as well as to evacuate reactant by-products from the chamber housing 100.
A control unit 110 is operably connected to the gas panel 130 and to the various operational components of the chamber housing 100, such as the vacuum pump 102 and the AC power supply 106, to control a CVD process carried out in the chamber housing 100. Control of process gases flowing through the gas panel 130 is facilitated by mass flow controllers (not shown) and a microprocessor controller (not shown). In a CVD process, the showerhead 120 facilitates a uniform distribution of process gases over the surface of a wafer W supported on the wafer support pedestal 150.
The showerhead 120 and the wafer support pedestal 150 form a pair of spaced-apart electrodes in the chamber housing 100. When an electric field is generated between these electrodes, the process gases flowing into the chamber housing 100 through the showerhead 120 are ignited to form a plasma. Typically, the electric field is generated by connecting the wafer support pedestal 150 to a source of RF (radio frequency) power through a matching network (not shown). Alternatively, the RF power source and the matching network may be coupled to the showerhead 120 or to both the showerhead 120 and the wafer support pedestal 150.
A remote plasma source 180 may be coupled to the chamber housing 100 to provide a remotely-generated plasma to the chamber housing 100. The remote plasma source 180 includes a gas supply 153, a gas flow controller 155, a plasma chamber 151 and a chamber inlet 157. The gas flow controller 155 controls the flow of process gases from the gas supply 153 to the plasma chamber 151.
A remote plasma may be generated by applying an electric field to the process gas in the plasma chamber 151, creating a plasma of reactive species. Typically, the electric field is generated in the plasma chamber 151 using an RF power source (not shown). The reactive species generated in the remote plasma source 180 are introduced into the chamber housing 100 through the inlet 157.
During the operation of the process chamber 10, when a material layer 103a is deposited over a wafer W supported on the wafer support pedestal 150, material residues 103b gradually accumulate on the interior surface S of the process chamber 10. The interior surface S of the process chamber 10 includes surfaces of elements exposed to the reaction gases or precursors. In some embodiments, the interior surface S includes the surface S1 of the chamber housing 100 and the surface S2 of the showerhead 120. Particles from the material residues 103b have a tendency to break off and potentially contaminate devices being fabricated on subsequent wafers processed in the process chamber 10, and therefore, must be periodically removed from the interior surface S for optimum processing.
Referring to
Referring to
In some embodiments, the process film P1 is a porous organosilicate glass (OSG) film deposited using a DEMS structure forming precursor and an ATRP pore forming precursor. In some embodiments, the process film P1 is a porous low-k layer having a dielectric constant of about 3.0 or less, about 2.6 or less, or about 2.0 or less.
Referring to
Referring to
In some embodiments, the non-process film NP1 is a substantially non-porous organosilicate glass (OSG) film deposited using a DEMS structure-former precursor. In some embodiments, the non-process film NP1 has a dielectric constant greater than that of the process film P1. In some embodiments, the non-process film NP1 has a dielectric constant of more than about 2.6, and preferably more than about 3.0.
Thereafter, in step 210, the process chamber 10 is idled for an idle time period before the next substrate or wafer is transferred into a process chamber 10. In some embodiments, in step 210, no precursor is introduced into the process chamber 10, as shown in
Referring to
In some embodiments, step 202 to step 210 constitute a deposition cycle 400 of the process chamber 10. Multiple deposition cycles 400 are performed until the predetermined number of wafers are respectively completed with their deposition steps. In some embodiments, there is no cleaning step between any two of step 202 to step 212. In some embodiments, there is no cleaning step in the repeating step 212.
Referring to
In the present disclosure, the deposition step of a non-process film, instead of the conventional chamber cleaning step, is provided between the deposition steps of process films of two adjacent wafers. The non-process film helps to adhere the underlying process film to the interior surface of the process chamber, and therefore prevents the film stack from peeling and contaminating a wafer that is processed in the chamber. The method of the present disclosure merely requires a single cleaning operation after multiple wafers are respectively deposited with process films in the chamber, and therefore, the chamber cleaning time can be significantly reduced.
In some embodiments, the present disclosure further provides a method of cleaning a process chamber as shown in
Referring to
In some embodiments, step (a) is first performed in the repeating step, and the film stack FS built up on an interior surface S of the process chamber 10 is shown in
In alternative embodiments, step (a) is last performed in the repeating step, and the film stack FS built up on an interior surface S of the process chamber 10 is shown in
In yet alternative embodiments, step (b) is first performed in the repeating step, and the film stack FS built up on an interior surface S of the process chamber 10 is shown in
After multiple wafers are respectively deposited with their process films in the same chamber, as shown in step (c) of
In some embodiments, the present disclosure also provides a method of cleaning a process chamber as shown in
Referring to
In some embodiments, as shown in
In some embodiments, the dielectric constant of the process films is different from (e.g., less than) the dielectric constant of the non-process films. In some embodiments, the dielectric constant of the process films is about 3.0 or less, and the dielectric constant of the non-process films is greater than about 3.0 and less than about 4.0. In alternative embodiments, the dielectric constant of the process films is about 2.5 or less, and the dielectric constant of the non-process films is greater than about 2.5. In yet alternative embodiments, the dielectric constant of the process films is about 2.0 or less, and the dielectric constant of the non-process films is greater than about 2.0.
In some embodiments, the porosity of the process films is different from (e.g., greater than) the porosity of the non-process films. In some embodiments, the process films are porous dielectric layers, and the non-process films are pore-free dielectric layers.
In some embodiments, the process films have a stress different from (e.g., greater than) the stress of the non-process films. In some embodiments, the process films are tensile dielectric layers, and the non-process films are compressive dielectric layers. The non-process films help to relieve the stress of the process films on the interior surface of the process chamber.
In some embodiments, a process film and a non-process film adjacent to the process film are in a thickness ratio of about 1:1 to 10:1. For example, the process film and the non-process film adjacent to the process film are in a thickness ratio of about 3:1 to 4:1. By controlling and adjusting the above thickness ratio within the range of the disclosure, the film stack can be stably adhered to the interior chamber surface before a chamber cleaning operation, and can be easily removed during the chamber cleaning operation.
After multiple wafers are respectively deposited with their process films in the same chamber, as shown in step (ii) of
The above embodiments in which two precursors are used in the chamber cleaning process are provided for illustration purposes, and are not construed as limiting the present disclosure. In some embodiments, more than two precursors can be used in the chamber cleaning process.
In some embodiments, the present disclosure further provides a method of cleaning a process chamber as shown in
Referring to
Specifically, the method of forming the process films and the non-process films includes introducing first pulses 312 and 314 of a first precursor 310 into the process chamber 10, introducing second pulses 322 of a second precursor 320 into the process chamber 10, and introducing third pulses 332 of a third precursor 330 into the process chamber 10. In some embodiments, the first pulses 312 and 314 of the first precursor 310 partially overlap with the second pulses 322 of the second precursor 320 and the third pulses 332 of the third precursor 330. For example, the first pulses 312 of the first precursor 310 overlapping with the second/third pulses 322/332 of the second/third precursor 320/330 and the first pulses 314 of the first precursor 310 not overlapping with the second/third pulses 322/332 of the second/third precursor 320/330 are arranged alternately. In some embodiments, the first precursor 310 is a film forming precursor, the second precursor 320 is a pore forming precursor, and the third precursor 330 is another pore forming precursor. In some embodiments, the first precursor 310 can be a silicon-rich precursor including methyldiethoxysilane (MDEOS) or diethoxymethylsilane (DEMS), and each of the second precursor 320 and the third precursor 330 can be a carbon-rich precursor including alpha-terpinene (ATRP), ethylene (C2H4) or a chemical corresponding to the general formula (CH3)2CHC6H6—CnH2n+1 (n is a positive integer).
After multiple wafers are respectively deposited with their process films in the same chamber, as shown in step (c) of
In view of the above, in the present disclosure, the deposition step of a non-process film, instead of the conventional chamber cleaning step, is provided between the deposition steps of process films of two adjacent wafers. The non-process films help to adhere the process films to the interior surface of the process chamber, and therefore prevent the film stack from peeling and contaminating a wafer that is processed in the chamber. After multiple wafers are respectively deposited with their process films in the same chamber, an extended cleaning operation is performed to completely remove the process films and non-process films from the interior surface of the process chamber. By such manner, the chamber cleaning time is significantly reduced, and the volume or throughput of wafers is greatly increased.
In accordance with some embodiments of the present disclosure, a method of cleaning a process chamber includes the following steps. A plurality of process films and a plurality of non-process films are alternately formed on an interior surface of the process chamber. A cleaning operation is performed to remove the plurality of process films and the plurality of non-process films from the interior surface of the process chamber.
In accordance with alternative embodiments of the present disclosure, a method of cleaning a process chamber includes the following steps. Step (a) of introducing a first precursor and a second precursor into a process chamber for a first time period and step (b) of introducing the first precursor into the process chamber for a second time period are repeated alternately m times, wherein m is an integer between 1 and 25, and a film stack is built up on an interior surface of the process chamber after step (a) and step (b) are repeated m times. A cleaning operation is then performed to remove the film stack from the interior surface of the process chamber.
In accordance with yet alternative embodiments of the present disclosure, a method of cleaning a process chamber includes the following steps. A substrate is transferred into a process chamber having an interior surface. Thereafter, a process film is deposited over the substrate, wherein the process film is also deposited on the interior surface of the process chamber. Afterwards, the substrate is transferred out of the process chamber. Next, a non-process film is deposited on the interior surface of the process chamber. The above steps are repeated m times, where m is an integer between 1 and 25. A cleaning operation is then performed to remove the process films and the non-process films from the interior surface of the process chamber.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
This is a continuation application of and claims the priority benefit of U.S. patent application Ser. No. 15/925,785, filed on Mar. 20, 2018, now U.S. Pat. No. 10,668,511.
Number | Name | Date | Kind |
---|---|---|---|
6090706 | Telford | Jul 2000 | A |
6413583 | Moghadam | Jul 2002 | B1 |
7713886 | Kobayashi | May 2010 | B2 |
8999847 | Furuta | Apr 2015 | B2 |
20030094377 | Krishna | May 2003 | A1 |
20040175957 | Lukas | Sep 2004 | A1 |
20050034996 | Horsthemke | Feb 2005 | A1 |
20050214455 | Li | Sep 2005 | A1 |
20050255714 | Iyer | Nov 2005 | A1 |
20060216952 | Bhanap | Sep 2006 | A1 |
20100298738 | Felts | Nov 2010 | A1 |
20140116338 | He | May 2014 | A1 |
20170062227 | Ishikawa | Mar 2017 | A1 |
20170159164 | Huang | Jun 2017 | A1 |
20190291145 | Lee | Sep 2019 | A1 |
Number | Date | Country |
---|---|---|
103290387 | Sep 2013 | CN |
102013100084 | Jul 2014 | DE |
0780488 | Jun 1997 | EP |
0845545 | Jun 1998 | EP |
2005-26687 | Jan 2005 | JP |
10-0447684 | Sep 2004 | KR |
10-2006-0024468 | Mar 2006 | KR |
10-2009-0025053 | Mar 2009 | KR |
WO 2012062467 | May 2012 | WO |
Entry |
---|
Fritzsche, H., et al., “Porosity and oxidation of amorphous silicon films prepared by evaporation, sputtering and plasma-deposition”. Solar Energy Materials, vol. 1, Issues 5-6, Jun.-Aug. 1979, 1 page. Abstract Only. |
Komiya, S., et al., “Titanium nitride film as a protective coating for a vacuum deposition chamber”. Thin Solid Films, vol. 63, Issue 2, Nov. 1, 1979, pp. 341-346. |
Agarwal, Ankur, et al., “Seasoning of plasma etching reactors: Ion energy distributions to walls and real-time and run-to-run control strategies”. J. Vac. Sci. Technol. A 26 (3), May/Jun. 2008, pp. 498-512. |
Thimmaiah, PoovannaCheppudira, et al., “A New Approach to Compute the Porosity and Surface Roughness of Porous Coated Capillary-Assisted Low Pressure Evaporators”. Scientific Reports (2018) 8:11708, pp. 1-11. |
Curran, J.A., et al., “Porosity in plasma electrolytic oxide coatings”. Acta Materialia 54 (2006) 1985-1993. |
Number | Date | Country | |
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20200290095 A1 | Sep 2020 | US |
Number | Date | Country | |
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Parent | 15925785 | Mar 2018 | US |
Child | 16886743 | US |