Claims
- 1. A method of making a semiconductor element comprising:
- a) forming a single-crystalline compound semiconductor substrate;
- b) preparing the substrate to have at least one rough surface having an average surface roughness within a range from 1 .mu.m to 20 .mu.m inclusive for reducing a risk of said substrate slipping in following step c);
- c) holding said substrate in a holding tool; and
- d) forming an epitaxial semiconductor layer on the rough surface of the substrate by liquid phase epitaxy.
- 2. The method of claim 1, wherein the average surface roughness is an average of a plurality of roughness values measured respectively at a plurality of measurement areas each having an area of about 1 cm.sup.2 on the rough surface, wherein each roughness value is a difference between a maximum surface height and a minimum surface height along a 1 mm long line within a respective one of the measurement areas, and wherein at least 50% of the roughness values are within a range from 1 .mu.mm to 20 .mu.m inclusive.
- 3. The method of claim 1, further comprising partially melting the rough surface before said step of forming an epitaxial layer.
- 4. The method of claim 3, wherein said partial melting comprises partially dissolving the rough surface in a solution of a raw material of the substrate.
- 5. The method of claim 1, further expressly excluding all lapping and polishing processes on the substrate prior to said step of forming an epitaxial layer.
- 6. The method of claim 1, wherein said steps of forming a substrate and preparing the substrate to have at least one rough surface together comprise slicing a substrate wafer from a single-crystalline ingot using a slicer.
- 7. The method of claim 6, further comprising a preliminary step of preparing the slicer by electrodepositing diamond abrasive grains on a grindstone.
- 8. The method of claim 1, wherein the substrate is prepared so that the rough surface has an average surface roughness within a range from 1 .mu.m to 10 .mu.m inclusive.
- 9. The method of claim 1, wherein the substrate is prepared so that the rough surface has an average surface roughness within a range from 2.0 .mu.m to 20 .mu.m inclusive.
- 10. The method of claim 1, wherein the substrate has a thickness in the range from about 370 .mu.m to about 600 .mu.m.
- 11. The method of claim 1, wherein said step of forming the epitaxial semiconductor layer is carried out so that the epitaxial layer has an n-type semiconductor layer and a p-type semiconductor layer.
- 12. The method of claim 1, wherein said step of forming the epitaxial layer is carried out so that the epitaxial layer has a thickness in the range from about 10 .mu.m to about 180 .mu.m, with a variation of the thickness being less than about .+-.5%.
- 13. The method of claim 1, wherein the epitaxial layer has an epitaxial growth start surface adjacent the rough surface and an epitaxial growth end surface opposite the growth start surface, and wherein the growth end surface is substantially smooth compared to the average surface roughness of the rough surface of the substrate.
- 14. The method of claim 1, wherein said step of forming a substrate comprises forming an intrinsic semiconductor material wafer, and said step of forming an epitaxial layer comprises forming a doped semiconductor layer.
- 15. The method of claim 1, wherein said step of forming a substrate comprises forming an intrinsic GaAs wafer, and said step of forming an epitaxial layer comprises forming a doped GaAs layer.
- 16. The method of claim 1, wherein said step of forming a substrate comprises forming a Zn-doped GaAs wafer, and said step of forming an epitaxial layer comprises forming an AlGaAs layer.
- 17. The method of claim 1, wherein the epitaxial layer has an epitaxial growth start surface adjacent the rough surface and an epitaxial growth end surface opposite the growth start surface, and wherein the growth end surface is smoother than the average surface roughness of the rough surface of the substrate.
- 18. A method of making a semiconductor element comprising:
- a) forming a single-crystalline compound semiconductor substrate;
- b) preparing the substrate to have at least one rough surface having an average surface roughness within a range from 2.0 .mu.m to 20 .mu.m inclusive for reducing a risk of said substrate slipping in following step c), wherein the average surface roughness is an average of a plurality of roughness values measured respectively at a plurality of measurement areas each having an area of about 1 cm.sup.2 on the rough surface, wherein each roughness value is a difference between a maximum surface height and a minimum surface height along a 1 mm long line within a respective one of the measurement areas, and wherein at least 50% of the roughness values are within a range from 2.0 .mu.m to 20 .mu.m inclusive;
- c) holding said substrate in a holding tool; and
- d) forming an epitaxial semiconductor layer on the rough surface of the substrate by liquid phase epitaxy.
- 19. A method of making a semiconductor element comprising:
- a) forming a single-crystalline compound semiconductor substrate;
- b) preparing the substrate to have at least one rough surface having an average surface roughness within a range from 1 .mu.m to 10 .mu.m inclusive for reducing a risk of said substrate slipping in following step c), wherein the average surface roughness is an average of a plurality of roughness values measured respectively at a plurality of measurement areas each having an area of about 1 cm.sup.2 on the rough surface, wherein each roughness value is a difference between a maximum surface height and a minimum surface height along a 1 mm long line within a respective one of the measurement areas, and wherein at least 50% of the roughness values are within a range from 1 .mu.m to 10 .mu.m inclusive;
- c) holding said substrate in a holding tool; and
- d) forming an epitaxial semiconductor layer on the rough surface of the substrate by liquid phase epitaxy.
Priority Claims (1)
Number |
Date |
Country |
Kind |
5-40336 |
Mar 1993 |
JPX |
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CROSS-REFERENCE TO RELATED APPLICATIONS
This is a divisional of U.S. patent application Ser. No. 08/400,271, filed Mar. 3, 1995, which issued as U.S. Pat. No. 5,514,903 on May 7, 1996, and which was a File Wrapper Continuation of U.S. patent application Ser. No. 08/204,059, filed Mar. 1, 1994 and now abandoned.
US Referenced Citations (7)
Foreign Referenced Citations (1)
Number |
Date |
Country |
63-256600 |
Oct 1988 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
400271 |
Mar 1995 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
204059 |
Mar 1994 |
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