Patent Application
20240120247
This application claims the benefit under 35 U.S.C. § 119(a) of European Application No. 22199970.9 filed Oct. 6, 2022, the contents of which are incorporated by reference herein in their entirety.
The present disclosure relates to a method of manufacturing a semiconductor package, such semiconductor package as well as an electronic system comprising a PCB element and at least such semiconductor package.
A known method of manufacturing a semiconductor device is disclosed in patent document U.S. Pat. No. 9,303,327B2. U.S. Pat. No. 9,303,327B2 further discloses a system, a packaged component, and a method for making a packaged component. In an embodiment of U.S. Pat. No. 9,303,327B2, a system comprises a component carrier, a component disposed on the component carrier and an insulating layer disposed on an electrically conductive surface of at least one of the component carrier or the component, wherein the insulating layer comprises a polymer and an inorganic material comprising a dielectric strength of equal or greater than 15 ac-kV/mm and a thermal conductivity of equal or greater than 15 W/m*K. Plating of a packaged component at the bottom side is disclosed. However, the resulting component does not have metal plated interconnection between the die and one of the leads (terminals).
A semiconductor device is disclosed in patent document U.S. Pat. No. 9,218,987B2, more precise a top-side cooled semiconductor package with stacked interconnection plate. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, and a moulding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang. The disclosed device of U.S. Pat. No. 9,218,987B2 relies on a 3D formed clip structure which needs to be assembled and needs additional parts to form a heatsink with the outside world.
Accordingly, it is a goal of the present disclosure to provide an improved semiconductor device with an integrated heatsink and electrical connection feature.
According to a first example of the disclosure, a method of manufacturing a semiconductor package having at least one semiconductor die connected with at least one conductive terminal is proposed. The semiconductor package has an upper side and a bottom side wherein at least one terminal is located at least partially on the bottom side. In particular, the method according to the disclosure comprises the steps of:
Finally, the method comprises the step of:
In an advantageous example of the method according to the disclosure, in step b) the semiconductor die is attached to the terminal using eutectic bonding preferably CuSn eutectic, Ag containing adhesives or Ag sintering material. These bondings are lead (Pb) free connection methods, which make the finished semiconductor package RoHS compliant (restriction of hazardous materials).
Additionally, step b) can be further implemented with the step wherein the semiconductor die is provided with a metallic or polymer bump or film protruding from the bottom side.
In two further preferred steps of the method according to the disclosure, the opening in the encapsulant is formed during the encapsulating process or the opening in the encapsulant is formed using a laser cutting process.
Additionally, step e) can encompass the application of galvanic plating process or the application of electroless plating process, or sputtering or any other means of depositing an electrically conductive material.
Furthermore in an example of the method, the semiconductor package is trimmed by cutting off a portion of the semiconductor package having a lead terminal, which trimming step is performed before step f). Alternatively, the semiconductor package is trimmed by cutting off a portion of the semiconductor package having a terminal after step f).
The disclosure also relates to a semiconductor package manufactured according to the method of the disclosure, with the semiconductor package having a semiconductor die which is connected with at least one of conductive terminals, wherein the semiconductor package has an upper side and a bottom side and wherein at least one terminal at least partially is located on the bottom side.
The disclosure also relates to an electronic system comprising a PCB element provided with solder pads and at least one semiconductor package manufactured according to the method of the disclosure, with the semiconductor package being attached with the terminals to the PCB element via the solder pads.
The disclosure will now be discussed with reference to the drawings, which show in:
For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.
With reference to
For the purpose of further usage in PCBs (Printed Circuit Board) or other electronics circuits, the semiconductor die 2 is connected with a plurality of conductive terminals 3. Those terminals 3 are protruding outside a semiconductor package 1 in any desired direction allowing mounting of the package 1 on a PCB and establishing electrical connections with the various terminals 3.
In another example, some terminals 3 are arranged in the manner that there is no part of terminal 3 protruding outside a semiconductor package 1, instead there are metallic (soldering enabled) parts of the terminals 3 exposed but not covered with the encapsulant 7 and accordingly suitable for being connected to the PCB using soldering alloy.
In this application, the phrase “terminal” is used in the meaning of any conductive layer outside of the semiconductor package 1 forming a pathway for the electric current or signal suitable for electrically connecting some part of the semiconductor package 1 with other parts of the electronic circuit (e.g. the PCB). Terminals 3 can also be referred as electrodes. A conductive layer 9, when connected to the terminal 3 or at least part of the die 2, can also be referred as terminal 3.
The semiconductor package 1 has an upper side 4 and a bottom side 5. However those sides are named only for easy reference and clarification as the semiconductor package 1 can be mounted to the PCB in different manners than here described.
In this example of a semiconductor package 1 of
Terminals 3, suitable for mounting the die 2, are sometimes referred as paddles having a wider end portion. In this example the terminals 3, which are suitable for attaching the die elements 2, are bend toward the upper side 4 so that during further attachment steps, the bottom surface of the die element 2 matches (or nearly matches) the height of the surface of another terminal 3.
In a next step b), the semiconductor die 2 is provided and electrically and mechanically attached to the terminal 3 of the lead frame 6, which is located at the bottom side 5. In certain examples, the die 2 can be attached to the terminal 3 using a conductive adhesive, or a Cu based alloy (e.g. CuSn eutectic alloy) or an Ag based glue or an alloy or any other known material, as long as the materials used are suitable for providing a mechanical and electrical connection between the die element 2 and the corresponding terminal 3.
In a further step c), an encapsulant 7 is provided over the semiconductor die 2 and the terminals 3, wherein a portion of the terminals 3 are left exposed. The exposed portion of the terminal 3 serves for a soldering spot to establish a solder joint (or conductive glue joint) with the final semiconductor package 1 and a PCB. On the bottom side 5, the encapsulant 7 may be provided with an opening 8, such that the semiconductor die 2 is partially exposed. This opening forms a spot for depositing a metallic layer, which layer connects to the die 2.
The opening 8 may be formed in the particular spot on the die 2 for connecting the terminal 3. In another example more than one opening 8 can be provided. In this example, the encapsulant 7 is a thermoplastic polymer provided over the die 2 using transfer molding techniques, and the opening 8 can be created during shaping of the injection mold. Other molding techniques can be implemented as alternative manufacturing techniques, such as compression molding or injection molding.
The injection form is shaped so that any injected encapsulant 7 is unable to cover the complete die element 2. Accordingly, during injection of the encapsulant 7, some spots are left uncovered and thus form the opening 8 as is shown in
A further step d) of the method according to the disclosure, pertains to cleaning the bottom side 5 of the semiconductor package in a wet process or a dry process. The cleaning process can also encompass or include a surface preparation step for the depositing of further metallic layers. It may also include the application of an surface activator material or solution.
The method according to the disclosure furthermore implements a step e) of partially plating a conductive layer 9 on the bottom side 5 in order to provide an electrically connection of the semiconductor die 2 via the opening 8 with the exposed portion of terminal 3, that is part of the terminal 3 being exposed from the encapsulant 7.
Finally, the method includes a singulating step f), wherein the semiconductor package 1 is separated from the lead frame 6. In this step some parts of the lead frame and terminals are removed (e.g. by trimming) and a final semiconductor package 1 is obtained, that matches the right standards. Some standards leave the terminals protruding the semiconductor package 1 (e.g. standards SOD123W, SOD323, SOD 323F) and some standards trim all the protruding terminals 3 off leaving only some part of the terminals 3 exposed thus not covered with encapsulant 7 (e.g. standard SOD882).
In another example of the disclosure, in step b) the semiconductor die 2 is provided with at least one metallic bump 10, which protrudes from the bottom side 5. This is also shown in
In the alternative example, during step c), the encapsulant 7 is formed (e.g. by means of transfer molding) completely over the die element 2 without leaving any opening 8. In this example of the method according to the disclosure, the process requires another step to form the opening 8, e.g. by using a laser cutting process. A laser device removes, cuts though or burns out the encapsulant 7 at the specifics spot over the die component 2 to form an opening 8 at the bottom side 5.
In yet another example of the disclosure, in step e) the terminal 3 which not previously connected to the die element 2, is connected with the die element 2 via the opening 8 by depositing an metallic layer over the terminal 3, the opening 8 and over the portion of the encapsulant 9 in between. This step can be performed by any known method of depositing a metallic layer, including a galvanic plating process or an electroless plating process.
In an alternative example of the disclosure, a spot plating Cu seed layer process is applied. This process provides a Cu seed layer with a thickness of up to 300 nm, on which Cu seed layer galvanic layers with a larger thickness can be deposited. In another alternative example, a sputter masked Cu layer deposition process is applied for this step. This process provides a Cu seed layer with a thickness of up to 3 μm on which galvanic layers with a larger thickness can be deposited. The seed layer can also be provided over the complete bottom side 5 using any know technique and subsequently, several parts of the seed layer are removed using a masked Cu etching process.
In a preferred example, the semiconductor package 1 is trimmed by cutting off a portion having a lead terminal of the semiconductor package 1 resulting in a semiconductor package 1 having reduced dimensions, as shown in
The disclosure also relates to a semiconductor package 1 having a semiconductor die 2 connected with a pair of conductive terminals 3. The semiconductor package 1 has an upper side 4 and a bottom side 5 wherein one terminal 3 is partially located on the bottom side 5. The semiconductor package 1 is manufactured in accordance with the process steps of the method of the disclosure as outlined above.
In another example, there may be two or more semiconductor dies 2 attached to the terminals 3, this example of implementing multiples dies 2 is shown in
The semiconductor package 1 as manufactured with the method according to the disclosure can be an element in an electronic system 11 (electronic device). The electronic system 11 may comprise a PCB element 12 provided with solder pads 13 and at least one semiconductor package 1 according to the disclosure, with the semiconductor package 1 being attached with the terminals 3 to the PCB element 12 via the solder pads. The PCB element 12 can be provided with a heatsink element placed (e.g. metal sheet) or formed (e.g. via thermal pads or via holes) nearby the opening 8 for improving any heat to be transferred from the die element 2 out of the semiconductor package 1.
| Number | Date | Country | Kind |
|---|---|---|---|
| 22199970.9 | Oct 2022 | EP | regional |
