Patent Application
20070072128
The present invention relates to the manufacture of semiconductor integrated circuits, and more specifically, to a method for improving element definition in a photolithography process.
Integrated circuit (IC) fabrication involves a process sequence in which patterns are generated in different material layers using, for example, a combination of deposition, lithography, and etching techniques. After the formation of a material layer on a silicon wafer, lithographic and etching techniques are used to transfer a desired pattern into the material, or to process the exposed substrate material. Typically, a radiation-sensitive material, called a resist, is spin-coated onto this material layer prior to lithographic printing. The lithographic printing step is usually performed using an imaging tool, which has a high intensity light source, a relay lens, a reticle stage, an imaging lens and a high precision translation stage.
A reticle containing an IC pattern to be printed is illuminated by a high intensity, high-frequency energy source such as a light source, which may be a mercury arc lamp or a laser, at a specific wavelength that causes radiation-induced changes in the resist. The light passing through the reticle is imaged by the lens onto the resist layer on the wafer. In one lithographic process in which a stepper is used, after each exposure, the wafer is stepped by a translation stage to the next site for subsequent exposure. The wafer is positioned on the translation stage. This exposure step essentially generates a latent image of the circuit pattern in the resist, similar to the exposure of a photographic film in conventional photography, hence the term photolithography. The exposed resist can then be developed to produce a patterned resist layer, which can be used as a mask in a subsequent processing step, which, for example, transfers this pattern onto the underlying material layer. While the process is described in terms of a stepper, it will be recognized that a scanning process, whole wafer printer, or FPD printer uses the same general equipment, and that the invention to be described herein is adaptable to each of these processes.
In general, each of the photolithography processes exposes a plurality of die on the wafer surface. This is accomplished by having a mask or reticle on which a plurality of separate patterns are formed. The focused radiation source which may be in the form described above, including an ultraviolet light source, then images the patterns onto the wafer at precise locations. The equipment carries the light source and exposes the IC pattern across the wafer in a predetermined time dependent manner. The stepper moves laterally, for example, from left to right, in “steps” across the width of the wafer to expose a predetermined number of die in one or more rows and columns of die at each step and then steps to a new position to repeat the process and expose another group of rows and columns of dies. At each step, a finite number of die are exposed to create one or more circuit features. The number of die patterns that may be duplicated on a reticle and which will define the number of die that can be exposed at each exposure position of the stepper is generally related to the size of each die and can vary from one to thirty or more. However, there is a practical limit to the number of devices that can be exposed at any step due to limitations in the depth of focus of the imaging radiation source. More particularly, a point source of radiation will have a focal plane in the shape of a portion of a sphere when projected through a simple lens. However, the wafer on which the reticle image is being focused is typically flat. The larger the area exposed at any step, the more likely there will be one or more die at the edge of the area of exposure that will not be in the best focus. As features of die become smaller, the depth of focus becomes smaller therein exacerbating the focus problem. Lack of focus results in poor line definition that can result in poor device performance and/or failure of the device created on the wafer. A more detailed description of such a lithographic process may be obtained from U.S. Pat. No. 6,218,077, which describes the process in terms of a scanning system rather than a stepper.
The clarity, or definition, of the IC pattern which is projected from the reticle is a function of the depth of focus at the wafer surface. As with any lens system, the focal depth becomes decreasingly smaller with increased resolution, i.e., as the dimensions of the focused features on the wafer become smaller, the focal depth decreases proportionately. Accordingly, in order to maintain focus over a realistic area of the wafer for each exposure, the area must be reduced thereby reducing the number of die that can be exposed at any time. Efforts to overcome this area limitation have typically been directed at lens solutions to flatten the focal plane at the wafer surface. These optical solutions generally have resulted in the focal plane either curving upward or downward at the corners of a rectangular exposure area. While it may be appreciated that the usefulness of the image that is projected through the mask is largely a function of the optics as provided by the stepper, the ability to obtain the projection of that image across a focal plane that provides uniform exposure onto the wafer is critical in order to maximize the efficiency of the manufacturing process.
It has been observed that often there occurs some degree of difficulty in obtaining a full and proper exposure of the wafer, and particularly at the edges thereof, in the manufacture of integrated circuits (ICs). This difficulty generally stems from an inability to obtain a necessary alignment of the focal plane, as provided by a projection of light from an imaging device, such as a stepper or scanner, and the wafer surface. When such alignment is achieved, it is likely that a full exposure will result.
In achieving such alignment, various methods have been used. Such methods have included the aligning of marks placed on each of the wafer and the mask, and also tilting of the wafer relative to the stepper. More importantly, efforts to achieve focus across the area of exposure have relied on optical solutions, i.e., adding more and more lenses (sometimes as many as 20 different lenses), in an effort to flatten the exposure plane to match the wafers flat surface. Notwithstanding each of these exemplary attempts concerning alignment, further advancements are needed to obtain a proper exposure across a large area of the wafer.
The issue of alignment, and its relation to obtaining proper exposure across a wafer surface, is best understood with reference to the FIGURES, wherein like reference numerals refer to like elements throughout. Referring to
During the exposure operation, both the reticle 22 and the wafer 26 are stationary when the resist 24 is exposed to the energy source 12 in a stepper system. For a discussion of scanning system operation, reference may be had to the aforementioned U.S. Pat. No. 6,218,077. The reticle translation stage 20 moves the reticle 22 in one or more directions and a wafer translation stage 29 moves the wafer 26 in one or more directions. For example, the reticle translation stage 20 and the wafer translation stage 29 may respectively move the reticle 22 and the wafer 26 along parallel to planes. Typically, the reticle translation stage 20 is moved relative to the wafer translation stage 28 in a straight line (the scanning direction) in a plane parallel to the major surface of the wafer, referred to herein as an X-Y plane.
The reticle translation stage 20, sometimes referred to as a stepper, is operated by a control apparatus 30, which also controls the position of the wafer translation stage 29. The pattern imaged through the lenses 14, 16 and 18 is received upon the energy sensitive photoresist (PR) 24 disposed on the wafer creating a change in the characteristics of the PR so as to transfer the patterns from the reticle to the PR. As will be understood by one skilled in the art, the stepper 10 will, in a predetermined time dependent manner, image all of the wafer 26 by stepping through an imaginary grid above the wafer surface to expose a plurality of dies on the wafer. The distance between the imaging lens 18 and the surface of the wafer 26 may be adjusted in a z-direction (orthogonal to the X-Y plane) to a desired focal plane by tilting or otherwise moving the wafer translation stage 29. Movement of the reticle translation stage 20, the wafer translation stage 29, and other components is implemented by the controller and drive mechanism 30. An exemplary scanning system of the type described in
In looking to
Referring to
While the majority of systems create a focal plane that is best fit by a concave wafer surface, as noted above, some optical solutions have resulted in a convex focal plane at the corners of the rectangular area of exposure through the mask or reticle. In such situations, the wafer can be distorted into a convex configuration by elevating the center of the wafer rather than the edge. The same approach of tilting could then be used to align the center of the area of exposure with the centerline through the reticle. In either the convex or concave solutions described above, the wafer can be distorted into the desired configuration by positioning a mechanical device under the wafer or by creating a shaped wafer carrier. The wafer can be held in the carrier using conventional techniques such as the aforementioned vacuum system.
It is to be understood that the optics, and particularly the lens through which the mask pattern is projected, will be suited to accomplish the conformance of the focal plane to the wafer surface as described herein, i.e., the optical system may have fewer lenses so that the focal plane conforms to the shape of
Thus, there is provided a method for manufacturing an IC using photolithography in which greater conformity is achieved between curvature on the wafer surface and the focal plane when patterning multiple integrated circuits onto the wafer.
While various embodiments of the present invention have been shown and described herein, such embodiments are provided by way of example only. Numerous variations, changes and substitutions may be made without departing from the invention herein. Accordingly, the invention is limited only by the scope of the appended claims.
