A specific embodiment according to the invention is described below with reference to the accompanying drawings.
Referring to
The etch-stop layer 22 and the interlayer insulating layer 21 are etched to form contact holes through which portions of the semiconductor substrate 20 are exposed. The contact holes are filled with a conductive layer to form lower contacts 23.
An oxide layer 24 is formed on the entire surface including the lower contacts 23. The oxide layer 24 may include a general oxide layer, but preferably includes an oxide layer to which F (fluorine) having a dielectric constant of about 3.7, which is lower than the dielectric constant of about 4.2 of a general oxide layer having is added (that is, an F oxide layer).
Referring to
Since the etch stop of the trenches 25 stops at the etch-stop nitride layer 22, the trenches 25 have a constant depth.
Referring to
The oxide layer 24 having a low dielectric constant is filled between the bit lines 26. A portion of the etch-stop nitride layer 22 having a high dielectric constant is small. Thus, in the case where bit lines having the same thickness are formed, the bit line capacitance can be decreased by about 10%.
In the prior art, the etch-stop nitride layer of about 300 Å in thickness and the oxide layer of about 1200 Å in thickness exist between the bit lines. Accordingly, an inter-bit line capacitance Cb is 300* the dielectric constant (8) of the nitride layer+1200* the dielectric constant (4.2) of the oxide layer, that is, about 7740.
In the invention, however, the nitride layer having a thickness h (refer to
Accordingly, when h is 150 Å, the inter-bit line capacitance becomes 6870. Accordingly, there is an advantage in that the inter-bit line capacitance is reduced by about 7.7%. When h is 100 Å, the inter-bit line capacitance becomes 6680. Accordingly, there is an advantage in that the inter-bit line capacitance is reduced by about 10.3%.
Furthermore, if FSG (dielectric constant of 3.7) having a low dielectric constant is used the oxide layer, the bit line capacitance can be reduced more effectively.
As described above, the invention has the following advantages.
After the etch-stop nitride layer is formed, the lower contacts are formed. When etching the trenches, a portion of the etch-stop nitride layer is etched in order to reduce the thickness of the nitride layer existing between the bit lines. Accordingly, bit line capacitance can be lowered and RC delay can be decreased.
Furthermore, an oxide layer to which fluorine (F) having a low dielectric constant is added used as the oxide layer. It is therefore possible to reduce inter-bit line capacitance and also to decrease RC delay.
The distinct embodiment of the invention is illustrative and not limiting. Various alternatives and equivalents are possible. Other additions, subtractions, or modifications are intended to fall within the scope of the inventions as defined in the appended claims.
Number | Date | Country | Kind |
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2006-58712 | Jun 2006 | KR | national |