Claims
- 1. A method of patterning a layer on sidewalls of a trench in a substrate for integrated circuits, said substrate being planar and horizontal, said method comprising the steps of:
- forming an insulator layer of a first composition on sidewalls of a trench in a substrate, said substrate having a horizontal top surface above said sidewalls;
- recessing a masking material in said trench below said top surface of said substrate, said masking material leaving an exposed portion of said insulator layer on said sidewalls of said trench exposed, said masking material and said substrate being of a different composition than said first composition; and
- etching said exposed portion of said insulator layer with a gaseous hydrogen flouride/ammonia mixture.
- 2. The method of claim 1 wherein said step of forming an insulator layer is performed by deposition.
- 3. The method of claim 1 further comprising the step of doping said insulator layer.
- 4. The method of claim 1 wherein said masking material is an organic photoresist.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional application of U.S. Ser. No. 08/865,261, now U.S. Pat. No. 5,838,055, filed May 29, 1997, and the complete contents of that application is herein incorporated by reference.
The patent application is related to the two concurrently filed patent applications bearing the titles of "VAPOR PHASE ETCHING OF OXIDE MASKED BY RESIST OR MASKING MATERIAL" and "OXIDE LAYER PATTERNED BY VAPOR PHASE ETCHING", respectively, and the complete contents of these two concurrently filed applications is herein incorporated by reference.
US Referenced Citations (14)
Non-Patent Literature Citations (1)
Entry |
T. K. Whidden, et al.; Catalyzed HF Vapor Etching of Silicon Dioxide for Micro- and Nanolithographic Masks; J. Electrochem. Soc., vol. 142, No. 4, Apr., 1995; pp. 1199-1205. |
Divisions (1)
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Number |
Date |
Country |
Parent |
865261 |
May 1997 |
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