Method to assess electromigration and hot electron reliability for microprocessors

Abstract

A method of assessing the tolerance of a microprocessor to propagation time degradation caused by electromigration effects and hot electron effects is provided. Reference values for interconnection resistance (IR) degradation and drain current (DC) degradation are compute, at nominal fabrication process and microprocessor lifetime application conditions. These results may be tabulated for a plurality of output driver load capacitances. Test IR degradation and test DC degradation values are calculated by scaling the reference IR and DC degradation values, respectively, for actual test conditions. The circuit propagation time and the propagation delay degradation caused by both electromigration and hot electron effects are calculated at process and lifetime environmental conditions. A timing equation is evaluated using distinctly identified components of the propagation delay degradation caused by electromigration and hot electron effects, to assess the toleration of the microprocessor to electromigration and hot electron induced propagation delay degradation.

Description

FIELD OF INVENTION

The present invention relates generally to microprocessor reliability analysis methods, and more particularly to methods for assessing microprocessor reliability while accounting for circuit propagation time degradation caused by electromigration and the hot electron effect.

BACKGROUND

Complementary metal oxide semiconductor (CMOS) microprocessors typically comprise one or more integrated circuit (IC) chips. Each IC chip includes thousands and perhaps millions of n-type field effect transistors (NFETS) and p-type field effect transistors (PFETS) which are used to construct memory arrays, latches, and other combinatorial logic elements. These circuits must reliably store or process data during every microprocessor cycle (t.sub.cycle) over the lifetime (.delta.) of the microprocessor.

The term electromigration (EM) refers to the transport of mass in metals when stressed to high current densities. EM occurs during the passage of direct current (DC) through thin metal conductors in integrated semiconductor integrated circuits, and results in accumulation of metal in some regions and voids in other regions. EM in extreme cases may be catastrophic with respect to circuit performance if either (i) accumulations become so severe as to bridge adjacent conductors, thereby causing short circuits, or (ii) voids become so severe as to cause open circuits. Such occasions are referred to as catastrophic faults.

Less catastrophic results (intermittent faults), but nonetheless problematic, results are possible due to partial void formation. Partial void formation causes changes in the interconnection resistance between transistors in the microprocessor circuit over time (see, e.g. A van der Ziel, "Two Different Methods of Determining Electromigration Parameters Associated with Resistance Change", Solid State Electronics, Vol 33, No. 8, pp 1025-1027 (1990)). This time dependent interconnection resistance degradation (.DELTA.R.sub.int (.tau.))/R.sub.int is proportional to circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd, because the time it takes for signals to traverse the interconnection paths between interconnected transistors depends on the interconnection resistance. Accordingly, EM effects which degrade interconnection resistance also degrade circuit propagation time. The circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd, in turn, may result in intermittent timing-faults, and reduce microprocessor reliability over circuit lifetime (.delta.) (Krautschneider, et al., "Reliability Problems of Submicron MOS Transistors and Circuits", Microelectron Reliability, Vol 32, No. 11, pp 1499-1508, (1992)). Both time dependent interconnection resistance degradation (.DELTA.R.sub.int (.tau.))/R.sub.int, and circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd are dependent on manufacturing process variations, circuit design, and microprocessor application factors of temperature, voltage and lifetime.

The term hot-electron (HE) effect refers to the phenomenon of electrons which originate from FET surface channel currents, from impact ionization currents at the FET drain junction, or from substrate leakage currents. Electrons drifting from the gate may gain sufficient energy to enter into the gate, or they may collide with the silicon atoms and generate electron-hole pairs. The hole adds to substrate current, and the secondary electron may be injected into the gate of a subsequent FET (see e.g., M. Annaratone, H.B. Digital CMOS Circuit Design, Kluwer Academic Publishers, Norwell Mass., p. 39, (1986)). As these secondary electrons accumulate in the gate, the FET threshold voltage shifts and the internal resistance of the device changes. Device current I.sub.d is proportional to both the internal resistance of the device and (V.sub.GS -V.sub.T).sup.2. Therefore, as the threshold voltage V.sub.T and the internal resistance changes, the current drive capability I.sub.d of the device changes. This time dependent, drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d must be less than 0.1 according to conventional hot-electron reliability criteria.

Drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d is a wear-out effect which reduces circuit reliability, because it also causes changes in circuit propagation time .DELTA.t.sub.pd (.tau.), which may result in intermittent timing-faults. Variances in the circuit propagation time, .DELTA.t.sub.pd (.tau.)/t.sub.pd, which are caused by this hot electron-induced drain current degradation effect, and the resulting changes in device internal resistance, are proportional to the time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d, which reduces microprocessor reliability over circuit lifetime (.delta.). Time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d and circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd are dependent on manufacturing process variations, circuit design, and microprocessor application factors of temperature, voltage and lifetime.

The hot electron and EM effects on propagation degradation are considered during circuit level design for each transistor (hot electron effect) and each transistor interconnect (EM effect) (see, e.g.T.J. O'Gorman, ADCHECK Circuit Reliability Program, IBM Microelectronics Division, May, 1994). The problem is that circuit-level analysis does not include the manner in which hot electron and EM effects are subsequently influenced by fabrication process variation, global wiring, and application factors such as temperature, voltage, and lifetime, or how these factors would be combined to optimize parametric yield.

Accordingly, when assessing microprocessor reliability, circuit designers must attempt to determine time dependent interconnection resistance degradation .DELTA.R.sub.int (.tau.))/R.sub.int, as well as time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d. Because both of these terms are proportional to variances in circuit propagation time .DELTA.t.sub.pd (.tau.)/t.sub.pd, the circuit designer may assess both interconnection resistance degradation and drain current degradation by analyzing .DELTA.t.sub.pd (.tau.)/t.sub.pd. Circuit propagation time degradation which is caused by EM and hot electron effects may then be used to determine if a particular circuit satisfies established timing criteria. In doing so, designers insure proper timing and amplitude of data and control signals propagating through the circuit, by insuring that the microprocessor may tolerate circuit propagation time degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd caused by both electromigration and hot electron effects.

SUMMARY

The present invention provides a means of assessment for time dependent interconnection resistance degradation, and time dependent drain current degradation, which accounts for manufacturing process variations, circuit design, and microprocessor application factors such as operating temperature, supply voltage and expected lifetime. The present invention is implemented in the form of a software analysis tool which may be used to assess the EM and hot electron reliability of a circuit. Reliability may be assessed across all of the circuits in an IC microprocessor chip, instead of merely at the circuit-level. The need to assess EM reliability may arise from a new design reliability audit, a change in technology standards, or an environmental use study.

In order to test microprocessor tolerance to propagation delay degradation caused by electromigration and hot electron effects, a reference interconnection resistance degradation and a reference drain current degradation must be computed at nominal fabrication process and microprocessor lifetime application conditions. The results of these computations are tabulated for a plurality of output driver load capacitances. A test interconnection resistance degradation and a test drain current degradation are then computed by scaling the reference values previously obtained to account for actual test conditions using actual process and lifetime environmental conditions.

Next, the circuit propagation time under these process and lifetime environmental conditions is calculated using known microprocessor logic and physical design data. The propagation delay degradation is calculated under these process, and lifetime environmental conditions while accounting for both electromigration and hot electron effects. The microprocessor tolerance to both the hot-electron and electromigration components of the induced propagation degradation is assessed using a timing equation which must be satisfied by the circuit design. Any circuits which violate timing equation may be redesigned and retested using this inventive method of analysis.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 (is a simplified circuit schematic of a microprocessor chip, the reliability of which may be tested by the present inventive method;

FIGS. 2 and 3 are flowcharts defining methods for assessing microprocessor tolerance to withstand circuit propagation delay degradation caused by EM and the hot electron effect, respectively;

FIG. 4 is a simplified schematic circuit-level model of a circuit used in the microprocessor of FIG. 1;

FIG. 5 is a network-level model of a plurality of circuits shown in FIG. 4 bound by registers;

FIG. 6 is a flowchart defining a method for assessing microprocessor tolerance to withstand circuit propagation delay degradation caused by both EM and the hot electron effect; and

FIG. 7 is a block diagram of a system constructed according to the principles of the present invention, including an analysis tool, various input files with which the analysis tool works, and an output file created by the analysis tool.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 1 represents a simplified circuit schematic of a microprocessor chip 10. A particular microprocessor may be made up of one or more of these chips 10, each of which may include millions of NFETS and PFETS, which form, for example, inverters and other logic elements or memory array elements. As shown in FIG. 1, the simplified microprocessor chip includes a digital signal generator 12 which operates at a predetermined frequency. The clock cycle corresponding to this frequency is referred to as the processor cycle time (t.sub.cycle).

The output of the signal generator 12 is a digital signal of varying amplitude and frequency which is sent to the gate of a CMOS inverter 14. The CMOS inverter 14 comprises a PFET 16 and NFET 18 the gates and drains of which are tied together. R.sub.tr,PFET represents the internal resistance of the PFET and R.sub.tr,NFET represents the internal resistance of the NFET. R.sub.tr as used later herein equals the electrical combination of R.sub.tr,PFET and R.sub.tr,NFET.

V.sub.dd is the power supply voltage for the inverter. The directions of current in the PFET and NFET of the inverter 14 which result from V.sub.dd are shown by the arrows labeled i. The NFET and PFET alternatively conduct through the t.sub.cycle of the signal generator 12. First, during the first half of the cycle, when PFFT 16 conducts, current flows from the power supply V.sub.dd through the PFET, and on through to R.sub.int and C.sub.load, where it accumulates (the charge path). During the second half of the cycle, this accumulated charge flows through R.sub.int and NFET 16 to ground (the discharge path). The drain current I.sub.d of the inverter 14 is the average of these two current flows, and is represented in the following formulae in terms of amps.

The output of the inverter 14 is sent to another circuit 20, which may be another inverter PFET/NFET pair, logic element or memory array element. The circuit 20 is represented as a capacitive load C.sub.load. An interconnection path 22 connects the output of the inverter 14 to the input of the circuit 20. The interconnection path is represented by the interconnection resistance R.sub.int and an interconnection capacitance C.sub.int. Changes in transistor resistance R.sub.tr are caused by EM effects and may be represented as a function of time (.tau.) with respect to EM effects. Changes in interconnection resistance R.sub.int are caused by hot electron effects and may be represented as a function of time (.tau.) with respect to hot electron effects.

The lifetime .delta. of the microprocessor chip 10 is equal to the total number of t.sub.cycle periods which the microprocessor is expected to provide. Microprocessor lifetime .delta. equals the sum of the microprocessor burn-in time (.tau..sub.burn-in) and field time (.tau..sub.field) operation of the chip. The cycle time of a circuit for each t.sub.cycle must satisfy the criteria: t.sub.cycle .gtoreq..SIGMA.t.sub.pd +B, where t.sub.pd =circuit propagation time for a given interconnection path and B=set-up, hold, and clock variation times (i.e. slack time) allotted for that path. In other words, ignoring the hot electron and EM effects on the circuit propagation time, the cycle time must be at least as great as the sum of circuit propagation time and the allotted slack time. In this manner, the proper design of a circuit insures that data and clock signals launched from a first logic circuit (e.g. inverter 14) may propagate through combinatorial logic and be captured at the next logic circuit by the occurrence of the next clock signal.

The tolerance of a microprocessor chip to withstand any circuit propagation time degradation, .DELTA.t.sub.pd (.tau.)/t.sub.pd, and thus its tolerance to withstand both interconnection resistance degradation caused by electromigration and drain current degradation caused by the hot electron effect, is assessed using the criteria:

t.sub.cycle -.SIGMA.[t.sub.pd .+-..DELTA.t.sub.pd (.tau.)]-B>0{eq.1}. According to equation 1, the t.sub.cycle time must be greater than the sum of (i) the slack time allotted for an interconnection path and (ii) the circuit propagation time for that path, which accounts for circuit propagation time degradation .DELTA.t.sub.pd (.tau.) due to both electromigration and hot electron effects. If it is not, timing equation 1 is violated. Equation 1, then, may be used to assess a microprocessor's tolerance to circuit propagation time degradation.

The following procedures, as described below with respect to the flow charts of FIGS. 2 and 3, outline the manner in which the tolerance of a microprocessor to withstand circuit propagation time degradation .DELTA.t.sub.pd (.tau.) is assessed[for degradation caused by both electromigration and hot electron effects.

Assessment of EM Induced Propagation Degradation

In order to assess the propagation time degradation .DELTA.t.sub.pd (.tau.) caused by electromigration effects, it is first necessary to determine the time dependent degradation in interconnection resistance, or .DELTA.R.sub.int (.tau.)/R.sub.int. The degradation of R.sub.int over time equals the sum of the unipolar currents in the drain charge current path and the uni-polar currents in the drain discharge current path in the circuit of FIG. 1. Accordingly,

.DELTA.R.sub.int (.tau.))/R.sub.int =[.DELTA.R.sub.d,CHARGE /R.sub.d,CHARGE ]+[.DELTA.R.sub.d,DISCHARGE /R.sub.d,DISCHARGE] {eq. 2}.

The time dependent interconnection resistance

R.sub.int (.tau.)=R.sub.int .+-..DELTA.R.sub.int (.tau.) {eq.3}, where R.sub.int is the initial start-of-life interconnect resistance, and .DELTA.R.sub.int (.tau.) represents interconnection resistance degradation of the initial start-of-life interconnect resistance which occur over time .tau. over microprocessor lifetime .delta.. R.sub.int is known from FIG. 1. Also from FIG. 1, assuming a uniform electric field and a constant electrical conductivity .sigma., it can be determined that R.sub.tr.C.sub.load =t.sub.pd =[length/(.sigma..multidot.area)].multidot.C.sub.load {eq. 4}; where conductivity .sigma.=.vertline.e.vertline..sup. .multidot.k.multidot.n/(m.multidot.T.sub.case) {eq. 5}; k, m, and n are process dependent constants; length and area are the dimensions of an interconnection segment under consideration; and (T.sub.case) is the microprocessor case temperature in degrees Centigrade. Accordingly, from equation 5, .DELTA.t.sub.pd (.tau.)=.DELTA.R.sub.tr (.tau.).multidot.C.sub.load{eq. 6}.

Both .DELTA.t.sub.pd (.tau.) and .DELTA.R.sub.int (.tau.))/R.sub.int are dependent on manufacturing process variation, circuit design, and microprocessor application factors of temperature, voltage and lifetime. Accordingly, a reference interconnection resistance degradation may be calculated as

.DELTA.R.sub.int,ref (.tau.)/R.sub.int,ref =(length/area).sup.k .times.(T.sub.case).sup.m .times.(.delta.).sup.n .times.exp(-k/I.sub.d){eq.7} at nominal fabrication process and microprocessor lifetime application conditions, including V.sub.dd, T.sub.case, t.sub.cycle, and L.sub.eff (effective channel length of both the PFET 16 and the NFET 18). Results of these calculations may be tabulated over a wide range of output driver load capacitances, C.sub.load. In doing so, a circuit designer may build a family of curves for various load capacitances. These various load capacitances represent a variety of devices which may comprise the circuit 20 in FIG. 1.

The reference interconnection resistance degradation is then scaled for actual test conditions to arrive at a test interconnection resistance degradation .DELTA.R.sub.int,test (.tau.))/R.sub.int,test using actual process and lifetime environmental conditions and the following formula:

.DELTA.R.sub.int,test (.tau.)/R.sub.int,ref =[.DELTA.R.sub.int (.tau.))/R.sub.int] .multidot.[(length.sub.test .multidot.area.sub.ref)/(area.sub.test .multidot.length.sub.ref].sup.k .multidot.[(T.sub.case,test)/(T.sub.case,ref)].sup.m.multidot.(.delta..sub.test)/(.delta..sub.ref)].sup.n .multidot.exp[(I.sub.d,test -I.sub.d,ref)/(I.sub.d,test .multidot.I.sub.d,ref)] {eq.8}. These environmental conditions effectively provide scaling factors which modify the reference interconnection resistance degradation reference previously computed for actual test conditions.

Now, the circuit propagation time t.sub.pd (.tau.) and the propagation delay degradation .DELTA.t.sub.pd (.tau.) may be computed under these same process and lifetime environmental conditions, and the values shown in FIG. 1. The term t.sub.pd (.tau.) may be computed using microprocessor logic and physical design data, and the term .DELTA.t.sub.pd (.tau.) is computed while accounting for electromigration effects. As shown in D. E. Moran, "Across-Chip Reliability Estimation", IEEE 1993 International Integrated Reliability Workshop Final Report, Oct. 24-27, 1993, t.sub.pd,test (.tau.)=(0.4.multidot.R.sub.int .multidot.C.sub.int)+[0.7.multidot.(R.sub.tr .multidot.C.sub.int +R.sub.tr .multidot.C.sub.load +R.sub.int C.sub.load)] which approximately equals (0.7.multidot.R.sub.tr 0.4.multidot.R.sub.int).multidot.C.sub.int for

C.sub.load <C.sub.int {eq. 9}.

Once the circuit propagation time under test conditions t.sub.pd,test (.tau.) is calculated, propagation delay degradation .DELTA.t.sub.pd,test (.tau.) may be subsequently computed as

.DELTA.t.sub.pd,test (.tau.)=[[(.DELTA.R.sub.d,CHARGE /R.sub.d,CHARGE).multidot.(t.sub.on/ (t.sub.on +t.sub.off))]+ [(.DELTA.R.sub.d,DISCHARGE /R.sub.d,DISCHARGE).multidot.(t.sub.on /(t.sub.on +t.sub.off))]].multidot.t.sub.pd,test (.tau.) {eq.10}.

With reference to FIG. 1, ton occurs on a rising edge of the signal output by the signal generator 12 and thus PFET 16 is ON and NFET 18 is OFF; t.sub.off occurs when the PFET is OFF and the NFET is ON.

Accordingly, t.sub.pd,test (.tau.) and .DELTA.t.sub.pd,test (.tau.) may be used in equation 1 to determine if the microprocessor chip 10 can tolerate the calculated electromigration induced propagation degradation .DELTA.t.sub.pd,test (.tau.). Circuits which are identified by this determination may be redesigned and then retested under the criteria established by equation 1: t.sub.cycle -.SIGMA.[t.sub.pd .+-..DELTA.t.sub.pd (.tau.)]-B>0. The preceding steps are outlined in the flowchart of FIG. 2.

Assessment of Hot Electron Induced Propagation Degradation

In order to assess the propagation time degradation .DELTA.t.sub.pd (.tau.) caused by the hot electron effect, it is first necessary to compute CMOS inverter 14 reference drain current degradation .DELTA.I.sub.d,ref (.tau.)/I.sub.d,ref. The reference drain current degradation for the inverter equals the sum of the NFET and PFET current degradation in the circuit. Thus,

.DELTA.I.sub.d,ref (.tau.)/I.sub.d,ref =.DELTA.I.sub.d,NFET (.tau.)/I.sub.d,NFET +.DELTA.I.sub.d,PFET(.tau.)/ I.sub.d,PFET{eq. 11}. The magnitude of the reference drain current degradation .DELTA.I.sub.d,ref (.tau.)/I.sub.d,ref is dependent on manufacturing process variations, circuit design, and microprocessor application factors of temperature, voltage and lifetime. The NFET current degradation may be computed as .DELTA.I.sub.d,NFET (.tau.)/I.sub.d,NFET =A.times.(L.sub.eff).sup.m .times..tau..sub.field.sup.n .times.exp(-k/V.sub.dd) {eq.12}, Where A is the area of an interconnection segment under consideration, k, m, and n are process dependent constants, V.sub.dd is in volts, and L.sub.eff is the effective channel length of the NFET in microns. Similarly, the PFET current degradation may be computed as .DELTA.I.sub.d,PFET (.tau.)/I.sub.d,PFET= A.times.(L.sub.eff).sup.m .times..tau..sub.field.sup.n .times.exp(-k/V.sub.dd) {eq.13}.

The reference current degradation is computed at nominal fabrication process and microprocessor lifetime application conditions, including V.sub.dd, T.sub.case, t.sub.cycle, and L.sub.eff (effective channel length of both the PFET 16 and the NFET 18). As with the results of the interconnection resistance reference degradation, results of these current degradation calculations may be tabulated over a wide range of output driver load capacitances, C.sub.load, so that the circuit designer may build a family of curves for various load capacitances.

Using the reference drain current degradation .DELTA.I.sub.d,ref (.tau.)/I.sub.d,ref from equation 11, the reference drain current degradation is then scaled for actual test conditions to arrive at a test drain current degradation .DELTA.I.sub.d,test (.tau.))/I.sub.d,test using actual process and lifetime environmental conditions and the following formula:

.DELTA.I.sub.d,test (.tau.)/I.sub.d,test =[.DELTA.I.sub.d,ref (.tau.))/I.sub.d,ref][(L.sub.eff,test)/(L.sub.eff,ref)].sup.m .multidot.[(.delta..sub.test)/(.delta..sub.ref)].sup.n .multidot.exp[(V.sub.dd,test -V.sub.dd,ref)/(V.sub.dd,test .multidot.V.sub.dd,ref)] {eq.14}. These environmental conditions effectively provide scaling factors which modify the drain current degradation reference previously computed for actual test conditions. Equation 14 affects microprocessor reliability because .DELTA.I.sub.d,PFET (.tau.)/I.sub.d,PFET increases to greater than unity over t.sub.burn-in, while .DELTA.I.sub.d,NFET (.tau.)/I.sub.d,NFET decreases to less than unity over t.sub.field. Thus, while a circuit is originally designed under the reference circuit propagation time t.sub.pd (.tau.) factor, decreases in t.sub.pd (.tau.) occur during t.sub.burn-in due to PFETs becoming faster, and increases in t.sub.pd (.tau.) occur during t.sub.field due to NFETs becoming slower.

Accordingly, the circuit propagation time t.sub.pd (.tau.) and the propagation delay degradation .DELTA..sub.pd (.tau.) is computed under these same process and lifetime environmental conditions, and the values shown in FIG. 1. The term t.sub.pd (.tau.) may be computed using microprocessor logic and physical design data, and the term .DELTA.t.sub.pd (.tau.) is computed while accounting for hot electron effects. As shown above,

t.sub.pd,test (.tau.)=(0.4.multidot.R.sub.int .multidot.C.sub.int)+[0.7.multidot.(R.sub.tr .multidot.C.sub.int +R.sub.tr .multidot.C.sub.load +R.sub.int .multidot.C.sub.load)] which approximately equals (0.7R.sub.tr +0.4 .multidot.R.sub.int).multidot.C.sub.int for C.sub.load <C.sub.int {eq. 9}. The effect of equation 9 is that it reduces microprocessor reliability because it erodes slack.

Once the circuit drain current under test conditions t.sub.pd,test (.tau.) is calculated, drain current degradation .DELTA.t.sub.pd,test (.tau.) may be subsequently computed as:

.DELTA.t.sub.pd (.tau.)=[[(.DELTA.I.sub.d,NFET /I.sub.d,NFET).multidot.(t.sub.on /(t.sub.on +t.sub.off))]+[(.DELTA.I.sub.d,PFET /I.sub.d,PFET).multidot.(t.sub.on /(t.sub.on +t.sub.off))]].multidot.t.sub.pd (.tau.) {eq.15}

In equation 15, .DELTA.I.sub.d,PFET (.tau.) is determined from equation 13, as well as from the following equations:

I.sub.d,PFET (.tau.)=.beta..multidot..sub.PFET .multidot.[(V.sub.in -(V.sub.dd -V.sub.t)).multidot.(V.sub.out -V.sub.dd)-0.5(V.sub.out -V.sub.dd).sup.2] {eq. 16}; and .DELTA.I.sub.d,PFET (.tau.)=.beta..multidot..sub.PFET .multidot.[(V.sub.in -(V.sub.dd -(V.sub.t .DELTA.V.sub.t,PFET))).multidot.(V.sub.out -V.sub.dd)-0.5(V.sub.out -V.sub.dd).sup.2 ], where .DELTA.V.sub.t,PFET= C.multidot.t.sub.burn-in.sup.p .multidot.exp((E.multidot..beta..sub.PFET.sup.m)-(D/V.sub.ds,NFET)){eq.17}. Also, in equation 15, .DELTA.I.sub.d,NFET (.tau.) is determined from equation 12. Thus, t.sub.pd,test (.tau.) and .DELTA.t.sub.pd,test (.tau.) may be used in equation 1 to determine if the microprocessor chip 10 can tolerate the hot-electron induced propagation degradation .DELTA.t.sub.pd,test (.tau.) (D. E. Moran, "Across-Chip Reliability Estimation", IEEE 1993 International Integrated Reliability Workshop Final Report, Oct. 24-27, 1993). Circuits which are identified by this determination may be redesigned and then retested under the criteria established by equation 1: t.sub.cycle -.SIGMA.[t.sub.pd .+-..DELTA.t.sub.pd (.tau.)]-B>0. The preceding steps are outlined in the flowchart of FIG. 3. Combined Assessment of EM/Hot Electron-Induced Propagation Degradation

The present invention also provides a method wherein the microprocessor tolerance to both the hot-electron and electromigration components of the induced propagation degradation .DELTA.t.sub.pd,test (.tau.) are determined in the same test.

Reliable microprocessor operation requires that the number of contacts and interconnect geometry across the chip may conduct the average equivalent dc current:

I.sub.dc,avg =(switching factor/t.sub.cycle).sctn.i(t)dt {eq.18}, over microprocessor lifetime .delta., where the magnitude of I.sub.dc,avg is dependent on process variation, chip design, and application factors of temperature, voltage and lifetime. The ability of a microprocessor to withstand catastrophic faults due to EM and hot electron effects is defined by the following: I.sub.dc,avg =C.sub.load .times.(dV.sub.load/ dt) , or approximately, I.sub.dc,avg =C.sub.load .times.0.5(V.sub.dd /t.sub.pd), (eq.19} where the catastrophic reliability criteria is that: [I.sub.dc,avg /(no. of contacts)]/[I.sub.dc,gr /contact]<1 for each network in the microprocessor circuit (see FIG. 5).

Because potentially millions of transistors may reside on a single microprocessor IC chip, each circuit in the chip is modeled as shown in the circuit 24 FIG. 4 as (i) a Boolean function 26 the design of which accounts for hot electron and EM effects, (ii) an output driver such as inverter 14 having a drive capability equal to I.sub.dc,avg, and (iii) an RC load comprising the interconnection resistance R.sub.int and the capacitance C.sub.load. The values for I.sub.dc,avg, R.sub.int , and C.sub.load, as well as the propagation delay t.sub.pd (.tau.) 0f the actual circuit, are available in the logic timing and chip physical design data. The subsequent consequences of process variations, chip design, and application factors on the hot electron and EM effects are assumed to act only upon the inverter 14.

The entire microprocessor chip is modeled as network 30 shown in FIG. 5 as n circuit level models (FIG. 4) bounded on each end by registers 28a and 28b. Next, the IC chip is partitioned into the total number of networks 30 used in the chip design. Accordingly, the data volume associated with evaluating the above identified equations is reduced to the process of evaluating a series of simple inverter networks, and repeating this process for the number of networks in the chip.

The partitioning of the IC chip into networks 30 realistically simplifies the circuit analysis, because the inverter 14 is most susceptible to hot electron effects due to its exposure to C.sub.load. Because the magnitude of these hot electron effects are directly proportional to device channel length (L.sub.eff) and inversely proportional to device channel width, the sufficiency of a given circuit is evaluated based on the C.sub.load it sees. The logic design timing simulation for circuit cycle time t.sub.cycle, circuit propagation delay t.sub.pd, circuit output driver specification, and circuit load capacitance C.sub.load is utilized in this process. The hot electron effect is used to simulate drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d over a range of output driver power-levels (V.sub.dd), output power channel lengths (L.sub.eff), and output loads (C.sub.load). Lastly, the system environment factors of power supply voltage (V.sub.dd), case temperature (T.sub.case), and lifetime .delta. are included in the calculations. The process steps associated with this procedure are outlined in the flowchart of FIG. 6.

FIG. 7 is a block diagram of a system 34 constructed according to the principles of the present invention, including an analysis tool 36, various input files 38, 40, and 42 with which the analysis tool works, and an output file 44 created by the analysis tool. As shown in FIG. 7, the input files and the output file take the form of hard disc storage, although other types of storage media are contemplated.

Input file 38 contains logic timing data taken from a logic design timing tool typically available to logic designers. The logic design timing tool creates this logic timing data based on analysis of circuit design parameters which represent the functional (timing) operation of the logic design, thereby enabling the logic designer a means of estimating the timing at the logic level (FIG. 4). Accordingly, input file 38 contains information relating to circuit inductance, R.sub.int, C.sub.load, t.sub.pd, t.sub.cycle, and B (slack information) for all register-bound networks on a chip. Such information relates to both the pre-physical and postphysical design of a microprocessor chip.

Input file 40 provides a degradation database containing information relating to the actual physical circuit design characteristics of a circuit (i.e. a physical design circuit library). This information results from timing measurements due to hot electron and EM effects, and may be provided by a commercially available physical device timing tool such as SPICE of ASTAP. The circuit-level timing tool permits circuit operation to be simulated using transistor and resistor models to determine the degradation effects which are to be expected for a particular circuit library. In this manner, a degradation database is created. The degradation database effectively calibrates the ERE analysis tool using the physical design circuit library under the expected degradation conditions.

The analysis tool 36 is termed ERE for early reliability estimator. The tool is implemented in the form of a software program which takes the logic timing data from the input file 38 and the degradation information provided by the input file 42 to calculate a reference interconnection resistance degradation for the interconnection resistance, and an inverter reference drain current degradation, under nominal fabrication process and microprocessor lifetime application conditions. The ETE tabulate these results of the reference current degradation and reference interconnection resistance degradation calculations for a plurality of output driver load conditions contained in the logic timing data file 38.

Next, the ETE computes drain current degradation and interconnection resistance degradation by scaling reference drain current degradation and reference interconnection resistance degradation, respectively, for actual test conditions using actual process and lifetime environmental conditions (actual use parameters). The scaling factors representing these actual use parameters are contained in input file 42.

Degradation of circuit propagation time contained in input file 38 is computed for each register-bound network in the microprocessor circuit (FIG. 5). Separate components of the propagation delay degradation are identified as resulting from electromigration effects, and from hot electron effects, under expected process and lifetime environmental conditions. The ETE then evaluates timing equation {1} using these propagation delay components to assess microprocessor toleration of electromigration and hot electron induced propagation delay degradation.

An output file 44 is created to store all of the information relating to drain current degradation, interconnection resistance degradation, and propagation delay degradation (i.e. a main degradation output file). Also stored is the identity of each of the circuits which violates equation {1} (i.e. a "flag" file). Other output files, of course, may be provided.

Based on the information in the output files 44, the circuit designer may either redesign the circuits which are in violation of equation {1} to provide for more slack time, or the circuit designer may slow down the speed of the chip by increasing t.sub.cycle so that equation {1} is satisfied. In the alternative, the circuit designer can do nothing, and merely rely upon the output files as a screening device to determine the reliability of a particular chip design.

Accordingly, the preferred embodiments of a method for assessing propagation time degradation in a microprocessor have been described. With the foregoing description in mind, however, it is understood that this description is made only by way of example, that the invention is not limited to the particular embodiments described herein, and that various rearrangements, modifications and substitutions may be implemented without departing from the true scope of the invention as hereinafter claimed.

Claims

1. A method of assessing propagation time degradation caused by electromigration effects in a microprocessor, wherein the microprocessor comprises a plurality of logic elements including at least a first logic element connected to a second logic element by an interconnection path having a time dependent resistance, and the propagation time degradation results from changes in the resistance over time, said method comprising the steps of:

calculating a reference interconnection resistance degradation for said interconnection resistance at nominal fabrication process and microprocessor lifetime application conditions;

tabulating the results of the reference interconnection resistance degradation calculations for a plurality of output driver load capacitances, said capacitances representing a variety of possible devices which may comprise the second logic element;

computing test interconnection resistance degradation by scaling the reference interconnection resistance degradation for actual test conditions using actual process and lifetime environmental conditions;

calculating the circuit propagation time under process and lifetime environmental conditions using microprocessor logic and physical design data;

calculating propagation delay degradation under process and lifetime environmental conditions while accounting for electromigration effects;

evaluating a timing equation using calculated circuit propagation time and propagation delay degradation to assess microprocessor toleration of calculated electromigration-induced propagation delay degradation; and

identifying circuits which violate said timing equation.

2. The method of claim 1, further comprising the step of redesigning and retesting identified circuits which violate said timing equation.

3. The method of claim 1, wherein said timing equation is:

t.sub.cycle -.SIGMA.[t.sub.pd .+-..DELTA.t.sub.pd (.tau.)]-B>0,

wherein t.sub.cycle is a microprocessor cycle time, t.sub.pd is a circuit propagation time for a given interconnection path, B represents set-up, hold, and clock variation times allotted for that path, and .DELTA.t.sub.pd (.tau.) is circuit propagation time degradation.

4. The method of claim 3, wherein said timing equation is evaluated for both intermittent and catastrophic faults.

5. A method of assessing propagation time degradation caused by hot electron effects in a microprocessor, wherein the microprocessor comprises a plurality of logic elements including at least a first logic element connected to a second logic element by an interconnection path having a time dependent resistance, said first logic element having a drain current, and the propagation time degradation results from changes in the drain current over time, said method comprising the steps of:

calculating an inverter reference drain current degradation at nominal fabrication process and microprocessor lifetime application conditions;

tabulating the results of the reference current degradation calculations for a plurality of output driver load capacitances;

computing test drain current degradation by scaling reference drain current degradation for actual test conditions using actual process and lifetime environmental conditions;

calculating the circuit propagation time under process and lifetime environmental conditions using microprocessor logic and physical design data;

calculating drain current delay degradation under process and lifetime environmental conditions while accounting for hot electron effects;

evaluating a timing equation using calculated circuit propagation time and propagation delay degradation to assess microprocessor toleration of calculated hot-electron-induced propagation delay degradation; and

identifying circuits which violate said timing equation.

6. The method of claim 5, further comprising the step of redesigning and retesting identified circuits which violate said timing equation.

7. The method of claim 5, wherein said timing equation is

t.sub.cycle -.SIGMA.[t.sub.pd .+-..DELTA.t.sub.pd (.tau.)]-B>0,

wherein t.sub.cycle is a microprocessor cycle time, t.sub.pd is a circuit propagation time for a given interconnection path B represents set-up, hold, and clock variation times allotted for that path, and .DELTA.t.sub.pd (.tau.) is circuit propagation time degradation.

8. The method of claim 7, wherein said timing equation is evaluated for both intermittent and catastrophic faults.

9. A method of assessing propagation time degradation caused by electromigration effects and hot electron effects in a microprocessor, wherein the microprocessor comprises a plurality of logic elements including at least a first logic element connected to a second logic element by an interconnection path having a time dependent resistance, said first logic element having a drain current, and the propagation time degradation results from changes in the resistance and drain current over time, said method comprising the steps of:

calculating a reference interconnection resistance degradation for said interconnection resistance, and an inverter reference drain current degradation, at nominal fabrication process and microprocessor lifetime application conditions;

calculating the results of the reference current degradation and reference interconnection resistance degradation calculations for a plurality of output driver load capacitances, said capacitances representing a variety of possible devices which may comprise the second logic element;

computing test drain current degradation and interconnection resistance degradation by scaling reference drain current degradation and reference interconnection resistance degradation, respectively, for actual test conditions using actual process and lifetime environmental conditions;

calculating the circuit propagation time under process and lifetime environmental conditions using microprocessor logic and physical design data;

calculating interconnection resistance degradation under process and lifetime environmental conditions while accounting for electromigration effects;

identifying a first propagation delay degradation component caused by electromigration effects under process and lifetime environmental conditions;

calculating drain current delay degradation under process and lifetime environmental conditions while accounting for hot electron effects;

identifying a second propagation delay degradation component caused by hot electron effects under process and lifetime environmental conditions;

evaluating a timing equation using said first and second propagation delay degradation components to assess microprocessor toleration of electromigration and hot electron induced propagation delay degradation; and

identifying circuits which violate said timing equation.

10. The method of claim 9, further comprising the step of redesigning and retesting identified circuits which violate said timing equation.

11. The method of claim 9, wherein said timing equation is:

t.sub.cycle -.SIGMA.[t.sub.pd .+-..DELTA.t.sub.pd (.tau.)]-B>0,

wherein t.sub.cycle is a microprocessor cycle time, t.sub.pd is a circuit propagation time for a given interconnection path, B represents set-up, hold, and clock variation times allotted for that path, and .DELTA.t.sub.pd (.tau.) is circuit propagation time degradation.

12. The method of claim 11, wherein said timing equation is evaluated for both intermittent and catastrophic faults.