Claims
- 1. A method of managing memory, comprising:
issuing a data request to remove data; determining whether the data is being removed from a cache line in a cache memory; determining whether the data being removed is stack data; and varying the memory management policies depending on whether the data being removed corresponds to a predetermined word in the cache line.
- 2. The method of claim 1, wherein the predetermined word is the first word in the cache line.
- 3. The method of claim 2, wherein the cache line is invalidated.
- 4. The method of claim 2, wherein the cache line holding the stack data is queued for replacement by a replacement policy when a read hit occurs on the first word of the cache line.
- 5. The method of claim 4, wherein the replacement policy is a least recently used (LRU) policy.
- 6. The method of claim 1, wherein the predetermined word is the last word in the cache line.
- 7. The method of claim 1, wherein the cache line is a dirty cache line.
- 8. The method of claim 7, further comprising, invalidating the dirty cache line if the predetermined word in the dirty cache line is the first word.
- 9. A system, comprising:
a memory; a controller coupled to the memory; a stack that exists in the memory; wherein the memory further comprises a cache memory and a main memory; and wherein the controller adjusts its management policies depending on whether data that is being removed corresponds to a predetermined word in a cache line.
- 10. The system of claim 9, wherein the predetermined word is the first word in the cache line.
- 11. The system of claim 10, wherein the cache line is invalidated.
- 12. The system of claim 11, wherein the invalidated cache line is queued for replacement by a replacement policy.
- 13. The system of claim 12, wherein the replacement policy is LRU.
- 14. The system of claim 9, wherein the predetermined word is the last word in the cache line.
- 15. The system of claim 9, wherein the cache line is a dirty cache line.
- 16. The system of claim 15, wherein the dirty cache line is invalidated if the predetermined word in the dirty cache line is the first word.
Priority Claims (1)
Number |
Date |
Country |
Kind |
03291915.1 |
Jul 2003 |
EP |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional Application Serial No. 60/400,391 titled “JSM Protection,” filed Jul. 31, 2002, incorporated herein by reference. This application also claims priority to EPO Application No. 03291915.1, filed Jul. 30, 2003 and entitled “Methods And Apparatuses For Managing Memory,” incorporated herein by reference. This application also may contain subject matter that may relate to the following commonly assigned co-pending applications incorporated herein by reference: “System And Method To Automatically Stack And Unstack Java Local Variables,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35422 (1962-05401); “Memory Management Of Local Variables,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35423 (1962-05402); “Memory Management Of Local Variables Upon A Change Of Context,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35424 (1962-05403); “A Processor With A Split Stack,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35425(1962-05404); “Using IMPDEP2 For System Commands Related To Java Accelerator Hardware,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35426 (1962-05405); “Test With Immediate And Skip Processor Instruction,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35427 (1962-05406); “Test And Skip Processor Instruction Having At Least One Register Operand,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35248 (1962-05407); “Synchronizing Stack Storage,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35429 (1962-05408); “Methods And Apparatuses For Managing Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35430 (1962-05409); “Write Back Policy For Memory,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35431 (1962-05410); “Mixed Stack-Based RISC Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35433 (1962-05412); “Processor That Accommodates Multiple Instruction Sets And Multiple Decode Modes,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35434 (1962-05413); “System To Dispatch Several Instructions On Available Hardware Resources,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35444 (1962-05414); “Micro-Sequence Execution In A Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35445 (1962-05415); “Program Counter Adjustment Based On The Detection Of An Instruction Prefix,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35452 (1962-05416); “Reformat Logic To Translate Between A Virtual Address And A Compressed Physical Address,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35460 (1962-05417); “Synchronization Of Processor States,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35461 (1962-05418); “Conditional Garbage Based On Monitoring To Improve Real Time Performance,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35485 (1962-05419); “Inter-Processor Control,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35486 (1962-05420); “Cache Coherency In A Multi-Processor System,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35637 (1962-05421); “Concurrent Task Execution In A Multi-Processor, Single Operating System Environment,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35638 (1962-05422); and “A Multi-Processor Computing System Having A Java Stack Machine And A RISC-Based Processor,” Ser. No. ______, filed Jul. 31, 2003, Attorney Docket No. TI-35710 (1962-05423).
Provisional Applications (1)
|
Number |
Date |
Country |
|
60400391 |
Jul 2002 |
US |