Patent Application
20150206813
The present disclosure, in various embodiments, relates generally to compositions including a silane material and related methods, such as for maintaining other materials (e.g., adhesives, underfill materials) in place using the silane material during processing of a semiconductor device.
Semiconductor devices and structures thereof are typically produced on a wafer or other bulk semiconductor substrate, which may be referred to herein as a “device wafer.” The array is then “singulated” into individual semiconductor devices, which may also be characterized as “dies” or “dice” that are incorporated into a package for practical mechanical and electrical interfacing with higher level packaging, for example, for interconnection with a printed wiring board. Device packaging may be formed on or around the die while it is still part of the wafer. This practice, referred to in the art as wafer-level packaging, reduces overall packaging costs and enables reduction of device size, which may result in faster operation and reduced power demand in comparison to conventionally packaged devices.
Thinning device wafer substrates is commonly conducted in semiconductor device manufacture because thinning enables devices to be stacked more easily while meeting dimensional constraints and enhances heat dissipation. However, thinner substrates are more difficult to handle without damage to the substrate or to the integrated circuit components thereon. To alleviate some of the difficulties, device wafer substrates are commonly attached to larger and more-robust carrier wafers. After processing, the device wafer substrates may be removed from the carrier wafers.
Common carrier materials include silicon (e.g., a blank device wafer), soda-lime glass, borosilicate glass, sapphire, and various metals and ceramics, among others. The carrier wafers are commonly substantially sized to match a size of the device wafer, so that the bonded assembly can be handled in conventional processing tools. Adhesives, such as polymeric adhesives, can be used for temporary wafer bonding are conventionally applied by spin coating or spray coating from solution or laminating as dry-film tapes. Spin- and spray-applied adhesives are increasingly preferred because they form coatings with higher thickness uniformity than tapes can provide. Higher thickness uniformity translates into greater control over cross-wafer thickness uniformity after thinning. The polymeric adhesives also exhibit high bonding strength to the device wafer and the carrier wafer.
During bonding, temporary adhesive may wick out from between the device wafer and the carrier substrate, and form on the carrier substrate. The adhesive that has wicked out is typically cleaned by a so-called “edge clean” process. Such a process may result in an undercut in the temporary adhesive bonding the device wafer to the carrier substrate where the edge of the device wafer is unsupported. The undercut increases the risk of wafer damage during subsequent processing, such as chemical-mechanical polishing (CMP). Though optimization is ongoing to design more-precise edge cleaning processes to reduce undercut, the temporary adhesive also tends to also wick when exposed to high temperature processes, such as CVD processes. Wicking of adhesive is problematic for some high temperature processes (e.g., PVD) because the presence of the excess adhesive results in non-uniform plating or complete failure to plate desired portions of the device wafer.
Another problem that may occur in forming semiconductor devices relates to the placement of underfill material. An underfill fillet may be used to cover an interface between a logic die and a DRAM stack. The material of the underfill fillet may extend over a surface of the logic die. If the material of the underfill fillet extends too far from the DRAM stack, the underfill fillet may interfere with the attachment of a conformal lid over the DRAM stack, resulting in reduced heat transfer from the DRAM stack and logic die and thermal degradation of the semiconductor dice of the package, resulting in not meeting operating temperature as well as thermal budget requirements.
In some embodiments disclosed herein, methods of processing a semiconductor device are described, as are semiconductor structures and compositions for use in semiconductor processing. Some methods include attaching a semiconductor substrate to a carrier substrate, forming a silane material on the carrier substrate, and stabilizing the silane material to form a hydrophobic coating on the carrier substrate. The hydrophobic coating may limit or prevent wicking of adhesive from between the semiconductor substrate and the carrier substrate during subsequent processing acts, and thus reduce or prevent undercut of the semiconductor substrate.
As used herein, the term “semiconductor substrate” means and includes a base material or construction upon which components, such as those of memory cells and peripheral circuitry, as well as logic, may be formed. The semiconductor substrate may be a substrate wholly of a semiconductor material, a base semiconductor material on a supporting structure, or a semiconductor substrate having one or more materials, structures, or regions formed thereon. The semiconductor substrate may be a conventional silicon substrate or other bulk substrate including a semiconductor material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates or silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si1-xGex, wherein x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), among others. Furthermore, when reference is made to a “semiconductor substrate” in the following description, previous process stages may have been utilized to form materials, regions, or junctions, as well as connective elements such as lines, plugs, and contacts, in the base semiconductor structure or foundation, such components comprising, in combination, integrated circuitry. Semiconductor substrates may also be, for example, a carrier wafer that does not have components formed therein.
As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (rotated 90 degrees, inverted, flipped, etc.) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, reference to an element as being “on” or “over” another element means and includes the element being directly on top of, adjacent to, underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to, underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
As used herein, the terms “comprises,” “comprising,” “includes,” and/or “including” specify the presence of stated features, regions, integers, stages, operations, elements, materials, components, and/or groups, but do not preclude the presence or addition of one or more other features, regions, integers, stages, operations, elements, materials, components, and/or groups thereof.
As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.
As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Embodiments are described herein with reference to the illustrations. The illustrations presented herein are not meant to be actual views of any particular material, component, structure, device, or system, but are merely idealized representations that are employed to describe embodiments of the present disclosure. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims.
The following description provides specific details, such as material types and processing conditions, in order to provide a thorough description of embodiments of the disclosed compositions and methods. However, a person of ordinary skill in the art will understand that the embodiments of the present disclosure may be practiced without employing these specific details. Indeed, the embodiments of the compositions and methods may be practiced in conjunction with conventional semiconductor fabrication techniques.
Any fabrication processes described herein do not form a complete process flow for processing semiconductor devices. Preceding, intermediary, and final process stages are known to those of ordinary skill in the art. Accordingly, only the methods and semiconductor structures necessary to understand embodiments of the present devices and methods are described herein.
Unless the context indicates otherwise, the materials described herein may be formed by any conventional technique including, but not limited to, dip coating, spin coating, spray coating, blanket coating, chemical vapor deposition (“CVD”), plasma-enhanced CVD, atomic layer deposition (“ALD”), plasma-enhanced ALD, or physical vapor deposition (“PVD”), as well as other deposition techniques known in the art. Alternatively, the materials may be grown in situ, unless the context otherwise indicates. Depending on the specific material to be formed, the technique for applying, depositing, growing, or otherwise forming the material may be selected by a person of ordinary skill in the art.
Disclosed are methods of processing semiconductor devices. The methods include bonding a semiconductor substrate to a carrier substrate, providing a silane material over an exposed portion of the carrier substrate, and solidifying the silane material to form a hydrophobic coating over the carrier substrate. The silane material may include a compound having a chemical formula selected from the group consisting of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, and (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer.
Reference will now be made to the drawings, where like numerals refer to like components throughout. The drawings are not necessarily to scale.
As shown in
The hydrophobic coating 106 may be a material formed, for example, by exposing the carrier substrate 102 and the semiconductor substrate 104 to a coat-forming composition. One or more components of the coat-forming composition may be reactive with one or more components of the carrier substrate 102 and/or the semiconductor substrate 104.
The coat-forming composition may include, for example and without limitation, a silane material. As used herein, the terms “silane” and “silane material” mean and include a chemical compound including silicon and at least one other element, e.g., carbon, hydrogen, nitrogen, sulfur, or a combination thereof. The silane material may be formulated as a non-functional silane or as a functional silane.
As used herein, the term “non-functional silane” means a silane material having an alkoxy group formulated to react with a metal material (e.g., in the carrier substrate 102) but lacking a functional group reactive with a nonmetallic material. Non-functional silanes may have stable functional groups connected to a silicon atom, such as phenyl groups, tolyl groups, alkyl groups, pentafluorophenyl groups, etc. Thus, non-functional silanes form a coating over the carrier substrate 102 that is relatively inert during conventional processing operations. Examples of non-functional silane materials include, but are not limited to, silane compounds including the formula —Si—(OC2H5)x, or —Si—(OCH3)x, wherein x is an integer, and including either a methoxy or an ethoxy group bonded to the Si atom. The methoxy or ethoxy group is hydrolyzable to form a silanol (i.e., a —Si—OH), and an alcohol (e.g., methanol or ethanol) may be formed as a by-product. Examples of such non-functional silanes include, without limitation, the materials listed and shown in Table 1, which table is not exhaustive.
As used herein, the term “functional silane” means a silane material formulated to react with the carrier substrate 102 and having a functional group reactive with a nonmetallic material of the carrier substrate 102. Functional silanes may have reactive functional groups directly or indirectly connected to a silicon atom, such as mercapto groups, sulfur groups, amine groups, epoxy groups, halogen groups, alkene groups, etc. Thus, functional silanes form a coating over the carrier substrate 102 that reacts during some conventional processing operations. For example, and without limitation, a functional silane material may be an organofunctional silane with one or more of the organofunctional groups or chemical structures in Table 2, which table is not exhaustive.
Examples of functional and non-functional silanes include, but are not limited to, a hybrid organic-inorganic compound with the formula (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, or (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO represents a hydrolyzable alkoxy group (e.g., methoxy, ethoxy), n represents an integer, and Y represents an organofunctional group, such as, for example, and without limitation, an alkyl, tolyl, phenyl, amino, sulfur, carboxyl, or thiol group. The organofunctional group Y may include various substitutions, such as halogens, hydroxyl groups, etc. Whether such materials are functional or non-functional depends on the characteristics of the organofunctional group Y. For example, if the organofunctional group Y includes fluorine-terminated groups (e.g., pentafluorophenyltriethoxysilane, as shown in Table 1), the material may be non-functional because the fluorine does not tend to react with other materials.
When a silane material, either functional or non-functional, is hydrolyzed in water, or, alternatively, in an alcohol and water mixture, silanol groups (i.e., Si—OH groups) may form. The silanol groups of the hydrolyzed coat-forming composition may be reactive with hydroxyl groups, such as those on the surface of a metal material or other material that has been exposed to oxygen and moisture. That is, exposure of a metal material or other material to oxygen may form oxides on the surface of the metal material or other material. Subsequent exposure of the formed oxides to moisture may form M-OH bonds, wherein M represents a metal (for example, and without limitation, Cu, Ni, Sn, Al, Ag) or Si. Thus, metal or silicon components of the carrier substrate 102 may include hydroxyl bonds on their surfaces. Exposure of such hydroxyl bonds to silanol groups of a hydrolyzed silane material may lead to reaction, e.g., a condensation reaction, of the hydroxyl groups with the silanol groups, forming M-O—Si bonds, wherein M represents a metal, or Si—O—Si. Accordingly, exposure of the carrier substrate 102 and/or the semiconductor substrate 104 to a coat-forming composition including a silane material, water, and, optionally, an alcohol, may enable reaction between the coat-forming composition and the surface of the carrier substrate 102 and/or the semiconductor substrate 104 to form the hydrophobic coating 106 on the metallic component wherein the coating includes M-O—Si bonds (metal-oxygen-silicon bonds) or Si—O—Si bonds (silicon-oxygen-silicon bonds).
Both functional and non-functional silane materials may be formulated to react with the carrier substrate 102 and/or the semiconductor substrate 104, as described above. Functional silane materials may be formulated to be additionally reactive. For example, in embodiments in which the silane material of the coat-forming composition includes an alkoxy (e.g., methoxy, ethoxy, etc.) group, the alkoxy groups of the silane material are hydrolyzable to form silanols that may react with the hydroxyl groups of the carrier substrate 102 and/or the semiconductor substrate 104. For example, and without limitation, the alkoxy groups of the silane material in the coat-forming composition may be hydrolyzed to silanols as illustrated in the following example reactions:
R′Si(OR)3+H2OR′Si(OR)2OH+ROH
R′Si(OR)2OH+H2OR′Si(OR)(OH)2+ROH
R′Si(OR)(OH)2+H2OR′Si(OH)3+ROH.
wherein R′ and R represent hydrocarbons. The silanols may then react with the hydroxides of the carrier substrate 102 and/or the semiconductor substrate 104 to form M-O—Si bonds or Si—O—Si bonds and water as illustrated in the following reaction, wherein the dashed line illustrates a surface of the carrier substrate 102 and/or the semiconductor substrate 104:
Examples of such alkoxy-including functional silane materials include, but are not limited to, monosilanes such as y-aminopropyltriethyoxysilanes (y-APS), y-methacryloxypropyltriethoxysilanes (y-MPS), or y-glycidoxypropyltrimethoxysilanes (y-GPS), and bis-silanes such as bis-[trimethoxysilylpropyl]amine (available under the name SILQUEST® A-1170 Silane from Momentive Performance Materials, Inc., of Columbus, Ohio), or bis[3-triethoxysilylpropyl]tetrasulfide (available under the name SILQUEST® A-1289 Silane from Momentive Performance Materials, Inc.).
The silane material of the coat-forming composition may alternatively or additionally be formulated to include other functional groups. For example, and without limitation, a functional silane material including sulfur functional groups may react with metal within the carrier substrate 102 and/or the semiconductor substrate 104, forming M-S bonds, also referred to herein as “metal-sulfur bonds.” For example, a sulfur group of a sulfur-based functional silane material may react with copper within the carrier substrate 102 and/or the semiconductor substrate 104 to form Cu—S bonds (“copper-sulfur bonds”). Therefore, such hydrophobic coating 106 formed may include M-S bonds.
Silanol groups of a silane material, whether functional or non-functional, may also condense with one another during formation of the hydrophobic coating 106, forming Si—O—Si bonds. The formation of the Si—O—Si bonds may increase the density and the viscosity of the coating material as the hydrophobic coating 106 forms. Therefore, the formed hydrophobic coating 106 may include Si—O—Si bonds.
The hydrophobic coating 106 may be formed by exposing surfaces of one or more materials of the carrier substrate 102 and/or the semiconductor substrate 104 to the coat-forming composition. The surfaces of the carrier substrate 102 and/or the semiconductor substrate 104 may be exposed to a solution that includes the coat-forming composition, and the surfaces of the carrier substrate 102 and/or the semiconductor substrate 104 may be dip-coated, spin-coated, spray-coated, or otherwise covered with the coat-forming composition.
Such a solution may include the coat-forming composition, a solvent, and, optionally, water. The solvent used in the solution may include a water-based solvent, a solvent miscible in water, and/or an organic solvent. For example, an organic solvent such as an alcohol (e.g., methanol, ethanol), in which the coat-forming composition is miscible, may be used to form the solution.
The solvent used in the solution may be selected such that the solution is formulated to reduce or prevent gelling of the coat-forming composition within the solution. As used herein, the term “gelling” means and includes thickening of the solution, increasing viscosity of the solution, and/or decreasing flowability of the solution prior to exposure of the carrier substrate 102 and/or the semiconductor substrate 104 to the solution. For example, use of an alcohol as the solvent may prevent gelling of the silane material and maintain flowability of the solution during application thereof on the carrier substrate 102 and/or the semiconductor substrate 104.
In some embodiments, the coat-forming composition may further include water (e.g., deionized water) to facilitate hydrolysis of the silane material to form the aforementioned reactive silanols. Water in the solution may also facilitate formation of oxide and hydroxyl groups on the carrier substrate 102 and/or the semiconductor substrate 104 when the carrier substrate 102 and/or the semiconductor substrate 104 are exposed to the solution. In other embodiments, the solution may be formed by mixing the coat-forming composition with the solvent in the absence of water. Water may then be introduced to the solution before the solution is applied to the surfaces of the carrier substrate 102 and/or the semiconductor substrate 104. In still other embodiments, the surfaces of the carrier substrate 102 and/or the semiconductor substrate 104 may be first exposed to water and then exposed to the other components (e.g., coat-forming composition and solvent) of the solution.
The solution may be formed by adding the coat-forming composition including the silane material to the solvent (e.g., alcohol), and then adding water (e.g., deionized water). During and following addition of the components to the solution, the solution may be stirred to inhibit gelling of the silane material.
The solution may be formulated to exhibit a pH in the range of from about 3 to about 10, such as from about 4 to about 9 prior to application of the solution on the carrier substrate 102 and/or the semiconductor substrate 104. Such pH ranges may reduce or prevent gelling of the coat-forming composition (e.g., silane material). A solution with a pH lower than about 3 or a pH greater than about 10, on the other hand, may facilitate gelling of the silane material before exposure of the carrier substrate 102 and/or the semiconductor substrate 104 to the solution. In some embodiments, an acid or a base may be added to the solution to maintain the pH in a selected range. For example, acetic acid may be added to the solution.
The solution may include from about 1% by volume to about 20% by volume of the coat-forming composition including the silane material, based on the total volume of the solution. For example, and without limitation, the solution may include from about 5% by volume to about 10% by volume of the coat-forming composition, from about 80% by volume to about 90% by volume ethanol or other alcohol-based solvent, and from about 5% by volume to about 10% by volume deionized water.
The average thickness of the hydrophobic coating 106 may be dependent upon the concentration of the silane material in the solution used to form the hydrophobic coating 106. For example, a solution with a higher concentration of silane material, relative to a solvent and, if present, other components of the solution, may result in a thicker hydrophobic coating 106 compared to a solution with a lower concentration of silane material. However, solutions including high concentrations of silane material may have a higher propensity to gel than those with lower concentrations of silane material. Therefore, the concentration of the silane material in the solution used to form the hydrophobic coating 106 may be tailored to achieve a hydrophobic coating 106 of a selected average thickness without excessive gelling. For example, and without limitation, a solution including at least about 5% by volume silane material, at least about 5% by volume deionized water, and a remainder ethanol or other alcohol-based solvent may be used to produce a hydrophobic coating 106 with a thickness from about 250 nanometers to about 500 nanometers. As another example, a solution including about 2% by volume of silane material may be used to produce a hydrophobic coating 106 with an average thickness of about 80 nanometers to about 200 nanometers.
Application of a solution may be self-limiting such that one application of the solution covers the exposed surfaces of the carrier substrate 102 and/or the semiconductor substrate 104 to saturation. However, in some embodiments, multiple applications of the solution may be performed to form a thicker coating or to ensure the coating is continuous. Exposure of the carrier substrate 102 and/or the semiconductor substrate 104 to the solution may be accomplished within a time frame of from about 30 seconds to about 1 minute, or longer if desired.
The solution may optionally include another material formulated to interact with the silane material, such as to increase the solubility, reduce or prevent gelling, or increase the hydrophobicity of the resulting hydrophobic coating 106. For example, other materials that may be present in the solution include a tetraethylorthosilicate (TEOS) of the formula Si—(OC2H5)4, colloidal alumina, etc.
After exposure of the carrier substrate 102 and/or the semiconductor substrate 104 to the coat-forming composition, either by way of direct exposure to the coat-forming composition or to a solution including the coat-forming composition, the coat-forming composition may be cured to stabilize the coat-forming composition. The curing conditions may depend on the silane material used as the coat-forming composition. For example, if the coat-forming composition includes a solvent, heating may cause evaporation of the solvent, leaving behind the hydrophobic coating 106. As another example, heating may cause a chemical reaction between components of the coat-forming composition or between a component of the coat-forming composition and the carrier substrate 102 and/or the semiconductor substrate 104. In some embodiments, the coating material may be cured at a temperature of at least about 100° C., at least about 125° C., or at least about 150° C. to form the hydrophobic coating 106. The cure temperature may be maintained for a period of time, such as for at least about ten (10) minutes, at least about thirty (30) minutes, or at least about one (1) hour. The cure time and temperature may be inversely related; to use a shorter cure time, a higher cure temperature may be used to achieve the same degree of cure. Curing the coat-forming composition may encourage reaction and bonding between the silane material and the carrier substrate 102 and/or the semiconductor substrate 104. The cure conditions may affect the properties of the hydrophobic coating 106, such as the density.
Thus, as shown in
A portion of the hydrophobic coating 106 may be removed from the semiconductor substrate 104 and/or the carrier substrate 102. For example, as shown in
In subsequent processing operations, additional semiconductor substrates 110 and/or additional circuit elements 108, such as transistors, diodes, capacitors, resistors, bond pads, lines, traces, through-wafer interconnects, dielectric material, etc., may be formed. For example, as shown in
As shown in
After removal of the hydrophobic coating 106, the semiconductor device 112 may be removed from the carrier substrate 102, as shown in
As shown in
As shown in
After removal of the hydrophobic coating 106, the semiconductor device 112 may be removed from the carrier substrate 102, as shown in
The hydrophobic coating 106 described herein may reduce or prevent adhesive 103 from wicking out from between the carrier substrate 102 and the semiconductor substrate 104 during processing. For example, if the circuit elements 108 (e.g., transistors, diodes, capacitors, resistors, bond pads, lines, traces, through-wafer interconnects, dielectric material, etc.) are formed by high-temperature processes, such as CVD or PVD, the hydrophobic coating 106 may keep liquefied adhesive material in place between the carrier substrate 102 and the semiconductor substrate 104. The hydrophobic coating 106 may also provide physical support for the semiconductor substrate 104 during subsequent processing operations such as chemical-mechanical polishing (CMP). Films subsequently formed over the semiconductor substrate 104 may adhere more uniformly because the hydrophobic coating 106 may reduce or prevent flaking of the carrier substrate 102 and/or the semiconductor substrate 104. The hydrophobic coating 106 may also help the carrier substrate 102 and the semiconductor substrate 104 to maintain contact with one another during processing. At least for these reasons, semiconductor devices 112 formed as described may have a higher uniformity and a lower defect rate than semiconductor devices formed by conventional methods.
The present disclosure also describes methods of processing a semiconductor device that includes forming a silane material over an exposed portion of a substrate and attaching at least one semiconductor device stack over the substrate. The semiconductor device stack may comprise one or more (e.g., two, four, eight, etc.) semiconductor device substrates. A surface of the semiconductor device stack may be in physical and thermal contact with the substrate. An underfill material may be provided between the semiconductor device substrates, and the silane material may be removed from the semiconductor substrate. For example, the methods may be used to contain an underfill material within a selected area, and to maintain an area of a semiconductor structure free of the underfill material. Thus, a lid may be more reliably and securely attached over the semiconductor structure to the area free of underfill material. The methods may be performed on an entire wafer or at the die level.
In some embodiments disclosed herein, a method may include attaching a semiconductor device stack to a substrate, forming a silane material over an exposed portion of the substrate, curing the silane material to form a hydrophobic coating over the carrier substrate, and providing an underfill material between the semiconductor device substrates over the semiconductor substrate.
A hydrophobic coating 212 may be provided over a portion of the logic die 202 such that a portion of the exposed surface of the logic die 202 remains exposed between the semiconductor device stack 208 and the hydrophobic coating 212. The hydrophobic coating 212 may be a silane material, as described above with respect to the hydrophobic coating 106 shown in
An underfill material 214 may be provided between the semiconductor substrates 204, 210. As shown in
Thus, a semiconductor device assembly may include a first semiconductor substrate, a semiconductor stack comprising one or more additional semiconductor substrates over a portion of the first semiconductor substrate, and a silane material over a portion of the first semiconductor substrate. An underfill material may be adjacent the additional semiconductor substrates (e.g., between two substrates) and over the first semiconductor substrate and between the silane material and the semiconductor stack. The silane material may comprise a compound having a formula selected from the group consisting of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, and (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer.
The hydrophobic coating 212 may be removed from the surface of the logic die 202, as shown in
In some embodiments disclosed herein, a method of forming a semiconductor device assembly includes forming a silane material on an exposed portion of a substrate, attaching a semiconductor device stack to the substrate, forming an underfill material between substrates of the semiconductor device stack, and removing the silane material from the substrate. The silane material comprises a compound having a chemical formula selected from the group consisting of (XO)3Si(CH2)nY, (XO)2Si((CH2)nY)2, and (XO)3Si(CH2)nY(CH2)nSi(XO)3, wherein XO is a hydrolyzable alkoxy group, Y is an organofunctional group, and n is a nonnegative integer. A surface of the semiconductor device stack may be in physical and thermal contact with the substrate.
As shown in
As shown in
An underfill material 214 may be provided between the semiconductor substrates 204, 210. As shown in
The hydrophobic coating 212 may then be removed from the surface of the logic die 202 and the substrate 200, as shown in
The logic die 202 may, in some embodiments, be a wafer or a portion of a wafer sufficient to receive multiple semiconductor devices. In such embodiments, the logic die 202 may be singulated at any point during processing. For example the logic die 202 may be singulated after removal of the resist 220, and before providing the semiconductor device stack 208.
The hydrophobic coating 212 may function to contain the underfill material 214 within selected boundaries on the logic die 202. Thus, a surface of the logic die 202 may remain free of the underfill material 214 such that the conformal lid 216 may be properly attached. At least for these reasons, semiconductor devices formed as described may have a higher uniformity and a lower defect rate than semiconductor devices formed by conventional methods.
While the disclosed device structures and methods are susceptible to various modifications and alternative forms in implementation thereof, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the present invention encompasses all modifications, combinations, equivalents, variations, and alternatives falling within the scope of the following appended claims and their legal equivalents.
