Patent Application
20120015113
The present invention relates generally to methods for forming low stress dielectric films. Embodiments of the present invention may be used, for example, in applications involving semiconductor devices, semiconductor substrate processing, flat panel displays (such as TFTs), masks and filters, energy conversion and storage (such as photovoltaic cells, fuel cells, and batteries), solid-state lighting (such as LEDs and OLEDs), magnetic and optical storage, micro-electro-mechanical systems (MEMS) and nano-electro-mechanical systems (NEMS), micro-optic and optoelectronic devices, architectural and automotive glasses, and micro- and nano-molding.
One of the primary steps in fabricating modern semiconductor devices is forming a dielectric layer on a semiconductor substrate. As is well known in the art, such a dielectric layer can be deposited by chemical vapor deposition (CVD). In a conventional thermal CVD process, reactive gases are supplied to the substrate surface where heat-induced chemical reactions take place to produce a desired film. In a conventional plasma enhanced CVD processes (PECVD), a plasma is formed to decompose and/or energize reactive species and promote reactions to produce a desired film. In general, reaction rates in thermal CVD and PECVD processes may be controlled using temperature, pressure, and/or reactant gas flow rates.
Increasingly stringent requirements for fabricating dielectric films, such as silicon oxides, are needed in order to produce high quality semiconductor devices. Many next-generation devices use vertical or 3D integration to increase device density. One challenge in vertical or 3D integration is forming thick silicon oxide layers that do not crack or peel. A layer that cracks or peels can cause defects that result in device failure. A film cracks or peels when a fracture energy of the film exceeds a cracking threshold. The fracture energy and cracking threshold depend in part on the thermal stress and thickness of the film. Thermal stress is measured at room temperature and results from differences in coefficients of thermal expansion between, for example, a film and an underlying substrate. Because the thermal stress for a particular film is generally constant for given deposition conditions, the cracking threshold is largely determined by deposition thickness. The deposition thickness at which the fracture energy is approximately equal to the cracking threshold can be called a critical thickness. Conventional silicon oxide deposition processes are unable to form silicon oxide films that exceed the critical thickness without cracking or peeling.
Thus, there is a need in the art for improved methods for forming thick silicon oxide films. These and other needs are addressed in the present application.
Embodiments of the present invention provide improved methods for forming silicon oxide films having low thermal stress that may be used, for example, in vertical or 3D integration. Such embodiments may be used to form thick silicon oxide layers that have low thermal stress and thus avoid cracking or peeling. The low thermal stress may be achieved by forming multi-layer silicon oxide films. As an example, a multi-layer silicon oxide film comprising thermal CVD layers and PECVD layers may be formed. The thermal CVD layers typically have a tensile thermal stress, while the PECVD layers typically have a compressive thermal stress. The thermal stress of the multi-layer silicon oxide film may be reduced compared to the absolute value of the thermal stress of the individual layers. Due to the reduced thermal stress, the thickness of the multi-layer silicon oxide film may be increased without exceeding the cracking threshold and causing cracking or peeling.
In accordance with an embodiment of the present invention, a method for forming a multi-layer silicon oxide film on a substrate includes depositing a first silicon oxide layer having a first thermal stress and a first thickness over the substrate using a thermal chemical vapor deposition (CVD) process. The first thermal stress and the first thickness provide a first fracture energy of the first silicon oxide layer that is less than a cracking threshold of the first silicon oxide layer. The method also includes depositing a second silicon oxide layer having a second thermal stress and a second thickness over the first silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The second thermal stress and the second thickness provide a second fracture energy of the second silicon oxide layer that is less than a cracking threshold of the second silicon oxide layer. The method also includes depositing a third silicon oxide layer having a third thermal stress and a third thickness over the second silicon oxide layer using the thermal CVD process. The third thermal stress and the third thickness provide a third fracture energy of the third silicon oxide layer that is less than a cracking threshold of the third silicon oxide layer. The method also includes depositing a fourth silicon oxide layer having a fourth thermal stress and a fourth thickness over the third silicon oxide layer using the PECVD process. The fourth thermal stress and the fourth thickness provide a fourth fracture energy of the fourth silicon oxide layer that is less than a cracking threshold of the fourth silicon oxide layer. The multi-layer silicon oxide film comprises the first silicon oxide layer, the second silicon oxide layer, the third silicon oxide layer, and the fourth silicon oxide layer, and a thermal stress and thickness of the multi-layer silicon oxide film provides a fracture energy of the multi-layer silicon oxide film that is less than a cracking threshold of the multi-layer silicon oxide film.
In accordance with another embodiment of the present invention, a method for forming a multi-layer silicon oxide film on a substrate includes performing a deposition cycle that comprises depositing a silicon oxide layer using a thermal chemical vapor deposition (CVD) process and depositing a silicon oxide layer using a plasma enhanced chemical vapor deposition (PECVD) process. The deposition cycle is repeated a specified number of times to form the multi-layer silicon oxide film comprising a plurality of silicon oxide layers formed using the thermal CVD process and a plurality of silicon oxide layers formed using the PECVD process. Each silicon oxide layer formed using the thermal CVD process is adjacent to at least one silicon oxide layer formed using the PECVD process.
Numerous benefits are achieved using the present invention over conventional techniques. For example, embodiments of the invention may be used to increase the thickness of a silicon oxide film without exceeding the cracking threshold and causing cracking or peeling. These and other benefits are described throughout the specification and more particularly below.
A further understanding of the nature and advantages of the invention may be realized by reference to the remaining portions of the specification and drawings. Like reference numerals are used throughout the several drawings to refer to similar components. In some instances, a sub-label is associated with a reference numeral and follows a hyphen to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.
The present invention provides methods for forming silicon oxide films having low thermal stress. As an example, an embodiment of the present invention provides a method of forming a multi-layer silicon oxide film. The multi-layer silicon oxide film may include layers formed using thermal CVD processes and layers formed using PECVD processes. The thermal stress of the thermal CVD silicon oxide layers is generally tensile, while thermal stress of the PECVD silicon oxide layers is generally compressive. The thermal stress of the individual thermal CVD and PECVD layers offset or counteract each other. This reduces an absolute value of the thermal stress of the multi-layer silicon oxide film compared to an absolute value of the thermal stress of the individual layers. The reduced stress increases the critical thickness of the multi-layer silicon oxide film. Thus, a thickness of the multi-layer silicon oxide film may be greater than a critical thickness of the individual layers of the film without causing cracking or peeling. Due to the reduced stress, the thickness can be increased before reaching the cracking threshold of the multi-layer silicon oxide film.
Silicon oxide layers formed using thermal CVD processes in accordance with embodiments of the present invention may use a variety of silicon precursors. Examples include silane (SiH4), dichlorosilane (DCS), tetraethylorthosilicate (TEOS), octamethylcyclotetrasiloxane (OMCTS), and the like. The silicon precursor may be mixed with an oxygen source (e.g., O2, ozone, etc.) and optionally a carrier gas (e.g., Ar, He, H2, and/or N2, etc.). The above compounds and elements are listed merely as examples and are not intended to be limiting. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
In an exemplary embodiment, the thermal CVD process is a sub-atmospheric CVD (SACVD) process using process gases that include TEOS, ozone, and N2. In one embodiment the TEOS flow may be in the range of about 1.0 gm to about 4.0 gm, the ozone flow may be in the range of about 10000 sccm to about 20000 sccm, and the N2 flow may be in the range of about 1000 sccm to about 5000 sccm. The temperature during the thermal CVD process may be in the range of about 200° C. to about 600° C., and the pressure may be in the range of about 200 Ton to about 760 Torr. Further details of exemplary thermal CVD processes that may be used in accordance with embodiments of the present invention are described in U.S. Pat. No. 5,963,840, entitled “Methods for Depositing Premetal Dielectric Layers at Sub-Atmospheric and High Temperature Conditions,” assigned to Applied Materials, Inc., the assignee of the present invention, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.
Silicon oxide layers formed using PECVD processes in accordance with embodiments of the invention may use a variety of silicon precursors. Examples include tetraethylorthosilicate (TEOS) hexamethyldisilane (HMDS) tetramethyldisiloxane (TMDSO), and the like. The silicon precursor may be mixed with an oxygen source (e.g., O2, ozone, etc.) and optionally a carrier gas (e.g., Ar, He, H2, and/or N2, etc.). The above compounds and elements are listed merely as examples and are not intended to be limiting. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
In an exemplary embodiment, the PECVD process may use process gases that include TEOS, O2, ozone, and He. In one embodiment the TEOS flow may be in the range of about 0.5 gm to about 3.0 gm, the O2 flow may be in the range of about 5000 sccm to about 10000 sccm, the ozone flow may be in the range of about 10000 sccm to about 20000 sccm, and the He flow may be in the range of about 5000 sccm to about 15000 sccm. The temperature during the PECVD process may be in the range of about 150° C. to about 600° C., and the pressure may be in the range of about 1 mTorr to about 20 Torr. The plasma may be formed either remotely or in situ using known plasma generation techniques.
An exemplary CVD process chamber in which embodiments of the method of the present invention can be carried out is shown in
CVD system 10 contains a gas distribution manifold 11 for dispersing process gases to a substrate (not shown) that rests on a heated pedestal or substrate support 12 centered within the process chamber. During processing, the substrate (e.g. a semiconductor wafer) may be positioned on a flat (or slightly convex) surface 12a of pedestal 12. The pedestal can be moved controllably between a lower loading/off-loading position (depicted in
Deposition and carrier gases may be introduced into chamber 15 through perforated holes of a conventional flat, circular gas distribution member or faceplate. More specifically, deposition process gases may flow into the chamber through the inlet manifold 11 (indicated by arrow 40 in
Before reaching the manifold, deposition and carrier gases may be input from gas sources 7 through gas supply lines 8 (
The deposition process performed in CVD system 10 may be a plasma-enhanced process. In a plasma-enhanced process, an RF power supply 44 may apply electrical power between the gas distribution faceplate and the pedestal so as to excite the process gas mixture to form a plasma within the cylindrical region between the faceplate and the pedestal. This region will be referred to herein as the “reaction region”. Constituents of the plasma may react to deposit a desired film on the surface of the semiconductor wafer supported on pedestal 12. RF power supply 44 may be a mixed frequency RF power supply that typically supplies power at a high RF frequency (RF1) of about 13.56 MHz and at a low RF frequency (RF2) of about 350 KHz to enhance the decomposition of reactive species introduced into the vacuum chamber 15. In a thermal process, RF power supply 44 would not be utilized, and the process gas mixture thermally reacts to deposit the desired films on the surface of the semiconductor wafer supported on pedestal 12, which may be resistively heated to provide thermal energy for the reaction.
CVD system 10 may also be used for thermal deposition processes. During a thermal deposition process, a heat transfer liquid may be circulated through the walls 15a of the process chamber to maintain the chamber at a constant temperature to prevent condensation of liquid precursors and reduce gas phase reactions that could create particles. A portion of these heat-exchanging passages in the lid of chamber 15 are shown in
The remainder of the gas mixture that is not deposited in a layer, including reaction byproducts, may be evacuated from the chamber by a vacuum pump (not shown). Specifically, the gases may be exhausted through an annular, slot-shaped orifice 16 surrounding the reaction region and into an annular exhaust plenum 17. The annular slot 16 and the plenum 17 may be defined by a gap between the top of the chamber's cylindrical side-wall 15a (including the upper dielectric lining 19 on the wall) and the bottom of the circular chamber lid 20. The 360° circular symmetry and uniformity of the slot orifice 16 and the plenum 17 help achieve a uniform flow of process gases over the wafer so as to deposit a uniform film on the wafer.
From the exhaust plenum 17, the gases flow underneath a lateral extension portion 21 of the exhaust plenum 17, past a viewing port (not shown), through a downward-extending gas passage 23, past a vacuum shut-off valve 24 (whose body may be integrated with the lower chamber wall 15a), and into the exhaust outlet 25 that connects to the external vacuum pump (not shown) through a foreline (also not shown).
The pedestal 12 (preferably aluminum, ceramic, or a combination thereof) may be resistively heated using an embedded single-loop heater element configured to make two full turns in the form of parallel concentric circles. An outer portion of the heater element may run adjacent to a perimeter of the support platter, while an inner portion may run on the path of a concentric circle having a smaller radius. The wiring to the heater element may pass through the stem of the pedestal 12. Typically, any or all of the chamber lining, gas inlet manifold faceplate, and various other reactor hardware are made out of material such as aluminum, anodized aluminum, or ceramic. An example of such a CVD apparatus is described in U.S. Pat. No. 5,558,717 entitled “CVD Processing Chamber,” issued to Zhao et al. and assigned to Applied Materials, Inc., the assignee of the present invention, and is hereby incorporated by reference in its entirety for all purposes.
A lift mechanism and motor 32 (
In some embodiments, the system controller may include a hard disk drive (memory 38), a floppy disk drive, and a processor 37. The processor may contain a single-board computer (SBC), analog and digital input/output boards, interface boards, and/or stepper motor controller boards. Various parts of CVD system 10 conform to the Versa Modular European (VME) standard, which defines board, card cage, and connector dimensions and types. The VME standard also defines the bus structure as having a 16-bit data bus and a 24-bit address bus.
System controller 34 may control all of the activities of the CVD machine. The system controller executes system control software, which may be a computer program stored in a computer-readable medium such as a memory 38. Preferably, memory 38 is a hard disk drive, but it may also include other kinds of memory. The computer program may include sets of instructions that dictate the timing, mixture of gases, chamber pressure, chamber temperature, RF power levels, susceptor position, and other parameters of a particular process. Other computer programs stored on other memory devices including, for example, a floppy disk or other another appropriate drive, may also be used to operate controller 34.
In the plot 200, dashed line 208 indicating a critical thickness or a thickness at a cracking threshold for the thermal CVD silicon oxide film 202 and the composite film 204. As shown in the plot 200, the thermal CVD silicon oxide film 202 has a critical thickness of about 1.4 μm. At this thickness, the thermal CVD silicon oxide film 202 has a thermal stress of about +275 MPa. The composite film 204 has a critical thickness of about 2.0 μm. At this thickness, the composite film 204 has a thermal stress of about +200 MPa.
In contrast, the multi-layer silicon oxide film 206 has a critical thickness greater than about 3.5 μm as indicated by the arrow in plot 200. In this example, the thermal stress of the multi-layer silicon oxide film 206 is about +25 MPa. Due to the low thermal stress, the critical thickness of the multi-layer silicon oxide film is higher than that of the thermal CVD silicon oxide film 202 or the composite film 204 as indicated by the dashed line 208. In this example, the thickness and stress of the multi-layer silicon oxide film 206 provide a fracture energy that is below the cracking threshold. Thickness of the multi-layer silicon oxide film 206 is increased by reducing thickness of the thermal CVD silicon oxide layers and PECVD silicon oxide layers below their respective critical thickness or cracking threshold values. Thus, an absolute value of the thermal stress of the multi-layer silicon oxide film 206 is less than an absolute value of the thermal stress of the individual thermal CVD and PECVD layers.
Listed in TABLE 1 below are thickness are stress results for exemplary multi-layer silicon oxide films formed in accordance with embodiments of the present invention. The exemplary films are formed using a specified number of deposition cycles. Each deposition cycle comprises a thermal CVD process and a PECVD process. Thus, each deposition cycle forms a thermal CVD layer and an adjacent PECVD layer. For example, the film in the first row was formed using four deposition cycles. As shown in TABLE 1, multi-layer silicon oxide films having a thickness of between about 2.9 μm and 3.5 μm were formed having a thermal stress of between about −2 MPa to about +30 MPa. In comparison, the thermal stress of the thermal CVD silicon oxide film 202 in
While the thermal CVD and PECVD processes may be formed in different processing chambers, forming the layers in situ in the same processing chamber is preferred to avoid the thermal stress associated with temperature cycling. Also, while each thermal CVD layer is generally formed using the same process conditions as other thermal CVD layers, such a limitation is not required. Similarly, each PECVD layer does not have to be formed using the same process conditions as other PECVD layers. The thermal stress and thickness of each thermal CVD and/or PECVD process may be determined based on the desired thermal stress and thickness of the multi-layer silicon oxide film.
As illustrated in
It should be appreciated that the specific steps illustrated in
While the present invention has been described in terms of specific embodiments, it should be apparent to those skilled in the art that the scope of the invention is not limited to the embodiments described herein. For example, it is to be understood that features of one or more embodiments of this invention may be combined with one or more features of other embodiments of the invention without departing from the scope of the invention. Also, examples and embodiments described herein are for illustrative purposes only, and various modifications or changes in light thereof will be evident to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
