Patent Application
20250046665
Example embodiments of the present disclosure generally relate to semiconductor devices and fabrication techniques. More specifically, the present disclosure relates to methods for improving passivation layer durability.
Some semiconductor devices may include layers of various materials, formed in a stack above a semiconductor substrate. Such semiconductor devices may be formed using a variety of techniques, such as photolithography, etching, deposition, doping, and other techniques. Such techniques may be utilized to form the various materials into patterns and configurations that enable the operation of the semiconductor device. In some cases, a semiconductor device may include various structures for coupling with other devices, such as other semiconductor devices. For example, a semiconductor device may include one or more layers formed in such a way that the semiconductor device may be coupled with another semiconductor device (e.g., via soldering, via flip-chip bonding). In some cases, a semiconductor device may include dissimilar materials with geometric discontinuities including interfaces, corners, and edges. Such semiconductor devices may be subjected to non-uniform thermal cycling during manufacturing, testing, storage, and operation. Due to differences in thermochemical properties of each material and geometric discontinuities, interfaces between materials may be prone to various types of failures, such as delamination.
Various embodiments described herein relate to methods, apparatuses, and systems for improving passivation layer durability. In one aspect, an apparatus includes a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate, one or more layers formed above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes circuitry, and a passivation layer formed above the one or more layers with respect to the third direction, the passivation layer including a plurality of cavities that each extend through the passivation layer, where the plurality of cavities and the circuitry are non-overlapping with respect to the first direction and the second direction.
In some embodiments, the one or more layers may include an insulating layer formed between the circuitry and the passivation layer, where each cavity of the plurality of cavities exposes a surface of the insulating layer. In some embodiments, each cavity of the plurality of cavities is formed in a shape of an elliptical cylinder including a height axis parallel to the third direction. In some embodiments, a ratio between a major axis and a minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern that includes uniform spacing between each cavity of the plurality of cavities. In some cases, all four sides of the rectangular pattern may have equal lengths (e.g., the rectangular pattern may be a square). In some other cases, sides of the rectangular patterns may have different lengths (e.g., the rectangular pattern may be a rectangle).
In some embodiments, the semiconductor substrate includes a silicon carbide material. In some embodiments, the one or more layers include a silicon carbide layer formed in contact with the semiconductor substrate, a metal layer formed at least partially in contact with the silicon carbide layer, and a silicon nitride layer formed at least partially in contact with the metal layer. In some embodiments, the circuitry may include transistor circuitry. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
In one aspect, a method may include forming a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate, forming one or more layers above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes circuitry, and forming a passivation layer above the one or more layers with respect to the third direction, the passivation layer includes a plurality of cavities that each extend through the passivation layer, where the plurality of cavities and the circuitry are non-overlapping with respect to the first direction and the second direction.
The method may also include forming the one or more layers including an insulating layer between the circuitry and the passivation layer, where each cavity of the plurality of cavities exposes a surface of the insulating layer. In some embodiments, forming each cavity of the plurality of cavities may include forming a cavity in a shape of an elliptical cylinder including a height axis parallel to the third direction. In some embodiments, a ratio between a major axis and a minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities. The method may also include forming the semiconductor substrate using a silicon carbide material.
In some embodiments, forming the one or more layers may include forming a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer at least partially in contact with the silicon carbide layer, and forming a silicon nitride layer at least partially in contact with the metal layer. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
In one aspect, a method for forming a product may include forming a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate, forming one or more layers above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes circuitry, and forming a passivation layer formed above the one or more layers with respect to the third direction, the passivation layer including a plurality of cavities that each extend through the passivation layer, where the plurality of cavities and the circuitry are non-overlapping with respect to the first direction and the second direction.
In some embodiments, forming the one or more layers may include forming an insulating layer between the circuitry and the passivation layer, where each cavity of the plurality of cavities exposes a surface of the insulating layer. In some embodiments, forming each cavity of the plurality of cavities may include forming a cavity in a shape of an elliptical cylinder including a height axis parallel to the third direction. In some embodiments, a ratio between a major axis and a minor axis of each elliptical cylinder is 3 to 1. In some embodiments, the plurality of cavities are arranged in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
In some embodiments, a non-transitory computer-readable storage medium may include instructions that when executed by a computer, cause the computer to form a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate, form one or more layers above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes circuitry, and form a passivation layer formed above the one or more layers with respect to the third direction, the passivation layer including a plurality of cavities that each extend through the passivation layer, where the plurality of cavities and the circuitry are non-overlapping with respect to the first direction and the second direction.
In some cases, forming the one or more layers may include form an insulating layer between the circuitry and the passivation layer, where each cavity of the plurality of cavities exposes a surface of the insulating layer. In some cases, forming each cavity of the plurality of cavities includes forming a cavity in a shape of an elliptical cylinder including a height axis parallel to the third direction. In some cases, the plurality of cavities are arranged in a rectangular pattern that includes uniform space between each cavity of the plurality of cavities. In some cases, forming the semiconductor substrate includes form the semiconductor substrate using a silicon carbide material.
In some cases, forming the one or more layers includes forming a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer at least partially in contact with the silicon carbide layer, and forming a silicon nitride layer at least partially in contact with the metal layer. In some cases, a ratio between a major axis and a minor axis of each elliptical cylinder is 3 to 1. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
In some embodiments, an apparatus includes a processor. The apparatus also includes a memory storing instructions that, when executed by the processor, configure the apparatus to form a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate, form one or more layers above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate, where at least a region of the one or more layers includes circuitry, and form a passivation layer formed above the one or more layers with respect to the third direction, the passivation layer includes a plurality of cavities that each extend through the passivation layer, where the plurality of cavities and the circuitry are non-overlapping with respect to the first direction and the second direction.
The apparatus may also be configured to form the one or more layers including forming an insulating layer between the circuitry and the passivation layer, where each cavity of the plurality of cavities exposes a surface of the insulating layer. The apparatus may also be configured to form each cavity of the plurality of cavities including forming a cavity in a shape of an elliptical cylinder including a height axis parallel to the third direction. The apparatus may also be configured to arrange the plurality of cavities in a rectangular pattern including uniform spacing between each cavity of the plurality of cavities. In some cases, forming the semiconductor substrate includes forming the semiconductor substrate using a silicon carbide material.
In some cases, forming the one or more layers includes form a silicon carbide layer in contact with the semiconductor substrate, forming a metal layer at least partially in contact with the silicon carbide layer, and forming a silicon nitride layer at least partially in contact with the metal layer. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims. In some cases, a ratio between a major axis and a minor axis of each elliptical cylinder is 3 to 1. Other technical features may be readily apparent to one skilled in the art from the following figures, descriptions, and claims.
The foregoing illustrative summary, as well as other exemplary objectives and/or advantages of the disclosure, and the manner in which the same are accomplished, are further explained in the following detailed description and its accompanying drawings.
The description of the illustrative embodiments may be read in conjunction with the accompanying figures. It will be appreciated that, for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale, unless described otherwise. For example, the dimensions of some of the elements may be exaggerated relative to other elements, unless described otherwise. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the figures presented herein, in which:
Some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. Indeed, these disclosures may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout.
As used herein, terms such as “front,” “rear,” “top,” etc. are used for explanatory purposes in the examples provided below to describe the relative position of certain components or portions of components. Furthermore, as would be evident to one of ordinary skill in the art in light of the present disclosure, the terms “substantially” and “approximately” indicate that the referenced element or associated description is accurate to within applicable engineering tolerances.
As used herein, the term “comprising” means including but not limited to and should be interpreted in the manner it is typically used in the patent context. Use of broader terms such as comprises, includes, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and comprised substantially of.
The phrases “in one embodiment,” “according to one embodiment,” and the like generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).
The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.
If the specification states a component or feature “may,” “can,” “could,” “should,” “would,” “preferably,” “possibly,” “typically,” “optionally,” “for example,” “often,” or “might” (or other such language) be included or have a characteristic, that a specific component or feature is not required to be included or to have the characteristic. Such a component or feature may be optionally included in some embodiments, or it may be excluded.
The material arrangement 100 may include a layer 105-a. The layer 105-a may be an example of a passivation layer, which may insulate or otherwise protect one or more layers 105 of the material arrangement 100 (e.g., layers 105 located below the layer 105-a with respect to the y-direction). In some cases, the layer 105-a may electrically insulate one or more layers of the material arrangement 100 or otherwise prevent the transmission of radio waves (e.g., electromagnetic fields) or electrical signals through the layer 105-a. The layer 105-a may also serve to protect the material arrangement 100 from incurring damage due to weathering or mechanical stresses. The layer 105-a may be formed using a material 110-a (e.g., a passivation material, an insulating material). In some cases, the material 110-a may be an example of polyimide, silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. The layer 105-a may be formed in contact with the layer 105-b.
The material arrangement 100 may include the layer 105-b. The layer 105-b may be an example of an insulating layer (e.g., a second insulating layer), which may be included in the material arrangement 100 (e.g., in addition to the layer 105-a) for improving adhesion of the layer 105-a. For example, the layer 105-a may more readily adhere to the layer 105-b than the layer 105-c. The layer 105-b may insulate or otherwise protect one or more layers 105 of the material arrangement 100 (e.g., one or more layers 105 located below the layer 105-b with respect to the y-direction). In some cases, the layer 105-b may electrically insulate one or more layers 105 of the material arrangement 100 or otherwise prevent the transmission of radio waves (e.g., electromagnetic fields) or electrical signals through the layer 105-b. The layer 105-b may be formed using a material 110-b, which may be an example of an insulating material such as polyimide, silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. In one illustrative example, the material 110-a may be polyimide and the material 110-b may be silicon nitride. In some other examples, however, the layer 105-a and the layer 105-b may be formed using a same material (e.g., polyimide). As described herein, the layer 105-b may be formed in contact with the layer 105-c, the layer 105-a, the layer 105-g, and the layer 105-d.
The material arrangement 100 may include the layer 105-c. The layer 105-c may be an example of a metallic layer, which may be utilized for routing electrical signals. The layer 105-c may be an example of a redistribution layer or any other type of conductive layer or conductive trace. The layer 105-c may be formed using the material 110-c. The material 110-c may be an example of copper, tungsten, aluminum, titanium, silver, or any other conductive material. As described herein, the layer 105-c may be formed in contact with any combination of the layer 105-b, the layer 105-d, and the layer 105-g.
The material arrangement 100 may include the layer 105-d. The layer 105-d may be an example of a semiconductor layer, which may be utilized for forming circuitry. The layer 105-d may include implant regions 115 (e.g., implant region 115-a, implant region 115-b, implant region 115-c). The implant regions 115 may be examples of doped regions of the layer 105-d and a depletion region of the layer 105-d. For example, the implant region 115-a may be an example of a ring implant region, which may be a region of the layer 105-d that is doped according to a specific process (e.g., n-type doping). The implant region 115-b may be an example of an anode implant region, which may be doped differently than the implant region 115-a (e.g., using p-type doping). The implant region 115-b may be an example of an anode or positive terminal for the material arrangement 100 (e.g., for a diode). The layer 105-d may also include the implant region 115-c, which may be an example of a depletion zone. The layer 105-d may be formed using the material 110-e (e.g., a semiconductor material). The material 110-e may be an example of silicon, silicon carbide, gallium arsenide, gallium nitride, indium phosphide, germanium, or any other semiconductor material. As described herein the layer 105-d may be formed in contact with the layer 105-e, the layer 105-c, the layer 105-g, and the layer 105-b.
The material arrangement 100 may include the layer 105-g. The layer 105-g may be an example of an oxide layer, which may provide electrical insulation. In some cases, the layer 105-g may be an example of an interlayer dielectric (ILD) or a gate dielectric. The layer 105-g may be formed using the material 110-d. The material 110-d may be an example of an oxide material, such as silicon dioxide, aluminum oxide, or any other dielectric material. As described herein, the layer 105-g may be formed in contact with the layer 105-b, the layer 105-c, and the layer 105-d.
The material arrangement 100 may include the layer 105-e. The layer 105-e may be an example of a semiconductor substrate. In some cases, the layer 105-c may be formed using the material 110-f The material 110-f may be an example of any semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium nitride, indium phosphide, germanium. In some cases, the material 110-f and the material 110-e may be different. In some other cases, however, the material 110-f and the material 110-e may be a same material, such as silicon carbide. As described herein, the layer 105-e may be formed in contact with the layer 105-d and the layer 105-f.
The material arrangement 100 may include the layer 105-f. The layer 105-f may be an example of a solder alloy layer. Although the layer 105-f is shown in
In some cases, the material arrangement 100 may be formed using one or more operations, such as lithography, etching, deposition, doping, metallization, soldering, or any other type of operation. In some cases, the layer 105-e may be deposited on the layer 105-f, the layer 105-d may be deposited on the layer 105-e, the layer 105-g may be deposited on the layer 105-d, and so forth. In some cases, the material arrangement 100 may include one or more layers 105 for coupling the layer 105-d, regions of the layer 105-d, or the layer 105-e (e.g., a redistribution layer) with circuitry of one or more other devices, such as another semiconductor device (not shown).
As described herein, the material arrangement 100 may include a variety of dissimilar materials with geometric discontinuities including interfaces, corners, and edges. The material arrangement 100 may be subjected to non-uniform thermal cycling during manufacturing, testing, storage, and operation. Due to differences in thermochemical properties of each material 110 and geometric discontinuities, interfaces between materials 110 (e.g., layers 105) may be prone to failure. In some cases, the layer 105-a (e.g., the passivation layer) that electrically insulates the stack of materials may be particularly prone to mechanical failure (e.g., delamination). Additional layers 105, such as the layer 105-b (e.g., silicon nitride), may be formed in contact with the layer 105-a to improve adhesion (e.g., between the layer 105-a and the layer 105-b). However, if a crack forms in the layer 105-b and delamination of the layer 105-a extends to the layer 105-c (e.g., the metal layer), electrical discharge may occur, as shown below.
The present disclosure provides techniques for improving the durability of layer 105-a by forming stress-relieving cavities through the layer 105-a. The cavities may be arranged along the periphery of the material arrangement 100. For example, the cavities may be located such that they do not overlap with the layer 105-c, the implant region 115-a, the implant region 115-b, or the implant region 115-c (e.g., in an x-z plane). For example, locations of cavities may be selected such that locations of the cavities in an x-z plane do note overlap with regions of the material arrangement 100 that include active circuitry. As described herein, locating cavities in regions that do not overlap with active circuitry of the material arrangement 100 may ensure that the active circuitry is effectively insulated by the layer 105-c (e.g., such that electromagnetic fields do not escape through the cavities). Additionally, each cavity may be formed in the shape of an ellipse (e.g., an elliptical cylinder) and may extend downward through the passivation layer (e.g., in the negative y-direction). Although examples described herein generally refer to cavities formed in the shape of ellipses, any cavity shape or geometry may be used. Similarly, relative distances between cavities, or the relative positioning of cavities may be modified based on one or more characteristics of the material arrangement 100.
The material arrangement 200-a may include one or more layers 205. For example, the material arrangement 200-a may include a layer 205-a (e.g., a passivation layer) and a layer 205-b. The layer 205-b may be an example of a layer 205 located below the layer 205-a with respect to the y-direction. The layer 205-b may be formed using the material 210-b. The material 210-b may be an insulating material, such as silicon nitride, silicon dioxide, aluminum oxide, or any other insulating material. In some other cases, the material 210-b may be a conductive material, such as aluminum. The layer 205-a may be formed using the material 210-a, which may be an example of an insulating material (e.g., different from the material 210-b). For example, the material 210-a may be an example of polyimide.
The layer 205-a may be formed around a periphery of a semiconductor device (e.g., a periphery of a material arrangement 200). In some cases, the layer 205-a may be formed by initially depositing the material 210-a (e.g., uniformly) on the layer 205-b. A center portion of the layer 205-a may then be removed, forming a void that exposes a top surface (e.g., with respect to the y-direction) of the layer 205-b (as shown in
As shown, the layer 205-a of the material arrangement 200-a may not include cavities 215 (e.g., peripheral cavities). Accordingly, non-uniform thermal cycling during manufacturing, testing, storage, and operation may result in mechanical stresses in the layer 205-a or between the layer 205-a and the layer 205-b. For example, increasing temperature may cause the layer 205-a and the layer 205-b to expand. However, the material 210-a may have a different coefficient of thermal expansion than the material 210-b, which may cause stress between the layer 205-a and the layer 205-b. Such stresses may increase the likelihood of delamination between the layer 205-a and the layer 205-b, which may lead to failure of the material arrangement 200-a.
In accordance with one or more aspects of the present disclosure, and as shown by the material arrangement 200-b, one or more cavities 215 may be formed in the layer 205-a, which may relieve stress (e.g., mechanical stress) in the layer 205-a or stress between the layer 205-a and the layer 205-b. As shown, the material arrangement 200-b may include a plurality of cavities 215 (e.g., the cavity 215-a through the cavity 215-jj). Each cavity 215 may expose a surface of the layer 205-b. Additionally, or alternatively, each cavity 215 may be formed in a location that avoids overlap with circuitry (e.g., active circuitry). For example, circuitry may be located within the region 220 (e.g., below the layer 205-b). Accordingly, cavities 215 may be formed outside of the region 220 (e.g., along the periphery of the material arrangement 200-b).
In accordance with one or more aspects of the present disclosure, each cavity 315 may be formed in the shape of an elliptical cylinder. For example, each cavity 315 may have a dimension 320-b (e.g., a minor diameter, a minor axis) and a dimension 320-c (e.g., a major diameter, a major axis). For one or more cavities 315 (e.g., the cavity 315-a, the cavity 315-b), the dimension 320-b may be parallel to the z-direction and the dimension 320-c may be parallel to the x-direction. However, the orientation of dimensions 320 for each cavity 315 may correspond to the orientation of each cavity 315. For example, the cavity 315-e may be oriented differently than the cavity 315-a. Accordingly, the dimension 320-b for the cavity 315-e may be parallel to the x-direction and the dimension 320-c for the cavity 315-e may be parallel to the z-direction.
Additionally, each cavity 315 may have a height dimension (not shown). The height dimension of each cavity 315 may be parallel to the y-direction. As described herein, each cavity 315 may extend through (e.g., fully) the layer 305-a. Additionally, or alternatively, cavities 315 may be spaced or located according to a dimension 320-a and a dimension 320-d. For example, the dimension 320-a may be an example of a distance between a respective cavity 315 (e.g., the cavity 315-a) and an extent of the layer 305-a. The dimension 320-a may be selected based on a location of circuitry. For example, the dimension 320-a may be selected such that each cavity 315 is located sufficiently far away from circuitry. Although not shown, the dimension 320-a may be the same for each cavity 315. That is, each cavity 315 may be located a same distance away from an extent of the layer 305-a. The dimension 320-d may represent a distance or spacing between respective cavities 315. In some cases, the dimension 320-d may be uniform for the plurality of cavities 315. That is, spacing between each cavity 315 may be the same.
The dimensions 320 may be determined based on a mathematical relationship, an algorithm, modeling, or test results. For example, a modeling operation may be performed to determine stresses present in the layer 305-a. The modeling operation may output various stress values for given dimensions 320. Accordingly, the modeling operation may select dimensions 320 such that one or more stresses in the layer 305 are minimized. In some cases, a specific ratio of the dimension 320-c to the dimension 320-b may be utilized. For example, the dimension 320-c may be approximately three times greater than the dimension 320-b. Such a ratio of the dimension 320-c to the dimension 320-b may be selected based on one or more stress values output by the modeling operation. For example, selecting the dimension 320-c to be approximately three times larger than the dimension 320-b may substantially reduce or eliminate stresses in the layer 305-a.
Although some examples described herein refer to cavities 315, some other examples may include forming (e.g., depositing) various materials 310 in cavities 315. For example, each cavity 315 may be filled (e.g., partially or fully) with a material 310 different from the material 310-a. For example, the material 310 may be configured for stress relief applications or may more generally have one or more properties that enable stress reduction in the layer 305-a. The material 310 may have a hardness or stiffness that is less than a hardness or stiffness of the material 310-a, which may enable the material 310 to release or eliminate stresses. For example, the material 310 may be relatively flexible when compared to the material 310-a. In some cases, one or more dimensions 320 may be selected or otherwise varied based on one or more dimensions of the material arrangement 300. For example, the dimensions 320 may be selected to scale with a size of the material arrangement 300. In some cases, one or more of the dimensions 320 may be selected or otherwise varied based on materials 310 selected for the material arrangement 300. For example, one or more of the dimensions 320 may be selected based on one or more properties of the material 310-a, the material 310-b, or both.
At 405, the method 400 may include forming a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate. The operations may be performed in accordance with examples as described herein. In some examples, aspects of the operations may be performed using a special-purpose machine or manufacturing system.
At 410, the method 400 may include forming one or more layers above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate. In some cases, at least a region of the one or more layers include circuitry (e.g., active circuitry). The operations may be performed in accordance with examples as described herein. In some examples, aspects of the operations may be performed using a special-purpose machine or manufacturing system.
At 415, the method 400 may include forming a passivation layer above the one or more layers with respect to the third direction. The passivation layer may include a plurality of cavities that each extend through the passivation layer. The plurality of cavities and the circuitry may be non-overlapping with respect to the first direction and the second direction. The operations may be performed in accordance with examples as described herein. In some examples, aspects of the operations may be performed using a special-purpose machine or manufacturing system.
At 505, the method 500 may include forming a semiconductor substrate elongated along a first direction and a second direction, the first direction parallel to a width of the semiconductor substrate and the second direction parallel to a depth of the semiconductor substrate. The operations may be performed in accordance with examples as described herein. In some examples, aspects of the operations may be performed using a special-purpose machine or manufacturing system.
At 510, the method 500 may include forming one or more layers above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate. In some cases, at least a region of the one or more layers include circuitry (e.g., active circuitry). The operations may be performed in accordance with examples as described herein. In some examples, aspects of the operations may be performed using a special-purpose machine or manufacturing system.
At 515, the method 500 may include forming an insulating layer between the circuitry and the passivation layer. Each cavity of the plurality of cavities may expose a surface of the insulating layer. In some cases, forming the one or more layers may include forming the insulating layer between the circuitry and the passivation layer. The operations may be performed in accordance with examples as described herein. In some examples, aspects of the operations may be performed using a special-purpose machine or manufacturing system.
At 520, the method 500 may include forming a passivation layer above the one or more layers with respect to the third direction. The passivation layer may include a plurality of cavities that each extend through the passivation layer. The plurality of cavities and the circuitry may be non-overlapping with respect to the first direction and the second direction. The operations may be performed in accordance with examples as described herein. In some examples, aspects of the operations may be performed using a special-purpose machine or manufacturing system.
While this detailed description has set forth some embodiments of the present invention, the appended claims also cover other embodiments of the present invention which may differ from the described embodiments according to various modifications and improvements. Within the appended claims, unless the specific term “means for” or “step for” is used within a given claim, it is not intended that the claim be interpreted under 35 U.S.C. 112, paragraph 6.
