This application claims the benefit of priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2006-0005554, filed Jan. 18, 2006, in the Korean Intellectual Property Office (KIPO), the disclosure of which is hereby incorporated herein by reference in its entirety.
1. Field of the Invention
Example embodiments of the present invention relate to methods of fabricating a semiconductor device. Other example embodiments of the present invention relate to methods of fabricating a semiconductor device using a metal nitride layer as a gate electrode.
2. Description of Related Art
A transistor is a semiconductor device that may be used for amplification, switching, voltage stabilization, signal modulation and many other functions. A transistor may include a gate electrode formed on an active region of a semiconductor substrate, a gate insulating layer interposed between the gate electrode and the semiconductor substrate and source/drain regions formed on the active region at both sides of the gate electrode. The gate insulating layer may be a silicon oxide layer (SiO2) formed by a thermal oxidation method. The gate electrode, contacting the gate insulating layer, may be a doped polysilicon layer. The transistor may be divided into an NMOS transistor and a PMOS transistor depending on a main carrier moving through a channel. In the NMOS transistor, the main carrier moving through the channel is an electron. In the PMOS transistor, the main carrier moving through the channel is a hole.
As semiconductor devices become more highly integrated, the gate insulating layer of the transistor may become smaller. The critical dimension of the gate electrode may also decrease. A thinner gate insulating layer and/or smaller critical dimension may be problematic. For example, leakage current may occur through the thinner gate insulating layer. Resistance of the gate electrode may increase according to a decrease in the critical dimension. A larger leakage current may occur in the PMOS region, compared to the NMOS region, due to a buried channel formed by doping.
In order to decrease the leakage current, the conventional art acknowledges a method of forming a gate insulating layer having a high-k dielectric layer. The high-k dielectric layer may be formed of a material having a higher dielectric constant than a silicon oxide layer. The dielectric constant of a silicon oxide layer is about 3.9. The high-k dielectric layer may be a material having a dielectric constant higher than about 3.9. When the gate insulating layer includes the high-k dielectric layer, it may be possible to form a gate insulating layer having a larger thickness compared to the silicon oxide layer, suppressing a leakage current.
In order to counteract any problems that may arise from an increase in resistance of the gate electrode, the conventional art acknowledges a method of forming the gate electrode having a metal nitride layer having a lower resistivity compared to a doped polysilicon layer. The metal nitride layer may be interposed between a gate insulating layer and a gate electrode formed on the doped polysilicon layer.
The gate electrode may be formed as a single polysilicon layer. A depletion region may be present in the gate electrode. Because the depletion region in the gate electrode may disappear, the gate electrode may be formed as a dual layer of metal nitride and polysilicon. An equivalent oxide thickness (EOT) of a high-k dielectric layer may decrease due to the gate electrode formed as the dual layer. The gate electrode formed in the dual structure may also exhibit an increase in capacitance.
When a metal layer is used for the gate electrode instead of the metal nitride layer, the metal layer may be oxidized by the high-k dielectric layer (e.g., gate insulating layer), deteriorating characteristics of a transistor.
The use of a high-k dielectric layer as a gate insulating layer and a metal nitride layer as a gate electrode are acknowledged in the conventional art.
According to the conventional art, a metal nitride layer may be formed on a substrate having a dielectric layer. The metal nitride layer may be a tantalum nitride (TaN) layer. A photosensitive layer pattern may be formed on the substrate having the metal nitride layer. The metal nitride formed of TaN may be exposed to a high density plasma using the photosensitive layer pattern as a mask. The high density plasma may be defined as a plasma having an electron density of at least 1011e31/cm3. The dielectric layer may be a high-k dielectric material having a high dielectric constant. The high density plasma may be generated from a gas source including a combination of a primary etchant gas and a profile-control additive. The fluorine gas may be a compound selected from the group consisting of CH4, NF3 and SF6 and a combination thereof. The gate electrode may be formed on the dielectric layer by exposing the metal nitride layer to the high density plasma. The high density plasma may etch the gate electrode.
The conventional methods may result in an undesirable etch profile of the metal nitride layer. The surface of the high-k dielectric layer may be damaged by the fluorine gas during the etching process of the metal nitride layer using the high density plasma. As a result, the desired characteristics of a gate insulating layer may not be obtained. In a recessed-type gate electrode, recessed portions may be also damaged.
In order to decrease the likelihood of forming an undesirable etch profile or the occurrence of damage during the etching process of the metal nitride layer using plasma, a method of removing the metal nitride layer by a wet etching process has been acknowledged.
Prior to forming a photosensitive layer pattern, a mask may be formed on the substrate having the metal nitride layer to remove the metal nitride layer. The mask may be used as an etch mask for etching the metal nitride layer. The mask may be an oxide layer. The mask may be formed using a thermal oxidation process, at a high temperature, to form the oxide layer and subsequently pattern the oxide layer. The oxide layer may be patterned to selectively cover a PMOS region. The metal nitride layer, exposed by the mask, may be removed by a wet etching process. The mask may be removed by the wet etching process. A fluoric acid solution may be used for wet-etching the mask.
When the metal nitride layer is removed using the wet etching process, problems that may occur during the plasma etching process may be resolved by a higher etch selectivity for the high-k dielectric layer. Because the oxide layer may be formed by the higher-temperature thermal oxidation method (during the wet etching process), the metal nitride layer may be denser due to the heat. As a result, an etch rate of the metal nitride layer may decrease and an etching time of the metal nitride layer may increase.
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Example embodiments of the present invention relate to methods of fabricating a semiconductor device. Other example embodiments of the present invention relate to methods of fabricating a semiconductor device using a metal nitride layer as a gate electrode.
Example embodiments of the present invention are also related to methods of fabricating a semiconductor device including forming a mask layer for etching a metal nitride layer using a low temperature process. The low temperature process may decrease the likelihood of altering characteristics of the metal nitride layer formed below the mask layer.
Other example embodiments of the present invention provide methods of fabricating a semiconductor device for reducing damages on a surface of a high-k dielectric layer when removing a mask.
In accordance with example embodiments of the present invention, a method of fabricating a semiconductor device is provided. The method may include providing a semiconductor substrate having a first region and a second region. A gate insulating layer, a metal nitride layer and/or an amorphous carbon layer may be sequentially formed on the substrate. The amorphous carbon layer may be selectively etched, forming an amorphous carbon mask covering the first region. The metal nitride layer exposed by the amorphous carbon mask may be etched, forming a preliminary metal nitride pattern. The amorphous carbon mask may be removed. The first region may be a PMOS region. The second region may be an NMOS region.
The metal nitride layer may be formed using chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process or any other process known in the art. The metal nitride layer may be formed having a thickness of about 50 Å to 150 Å. The metal nitride layer may be a TaN layer or a TiN layer.
The amorphous carbon layer may be formed using a CVD process. The amorphous carbon layer may be formed having a thickness of about 2000 Å to 5000 Å. The deposition process may be performed at a temperature of about 200° C. to 400° C. After forming the amorphous carbon mask, nitrogen impurities may be implanted into the metal nitride layer exposed by the amorphous carbon mask.
The etching of the metal nitride layer may be performed using a wet etching. The wet etching may be performed at a temperature of about 25° C. to 80° C.
The amorphous carbon mask may be removed using an ashing process.
The gate insulating layer may be a high-k dielectric layer. The high-k dielectric layer may be formed of a compound selected from the group consisting of HfO2, HfSiO, TiO2, Ta2O5 and ZrO2.
After removing the amorphous carbon mask, a conductive layer may be formed on the substrate having the preliminary metal nitride pattern. The conductive layer and the preliminary metal nitride pattern may be sequentially etched to form a conductive pattern and a metal nitride pattern, respectively. A first gate electrode having the metal nitride pattern and the conductive pattern doubly stacked may be formed in the first region. A second gate electrode may be formed in the second region. The second gate electrode may be formed from the conductive pattern.
Alternatively, the conductive layer and the preliminary metal nitride pattern may be sequentially etched, forming a first gate electrode and a second gate electrode in the first region and the second region, respectively.
After forming the first gate electrode and the second gate electrode, source/drain regions may be formed in the substrate at sides of the first gate electrode and the second gate electrode, respectively.
In accordance with other example embodiments of the present invention, another method of fabricating a transistor is provided. The method includes forming a semiconductor substrate having a first region and a third region. The first region may be a PMOS region and the third region may be a NMOS region, or vice versa. A gate insulating layer, a metal nitride layer and/or an amorphous carbon layer may be sequentially formed on the semiconductor substrate. The amorphous carbon layer may be selectively etched, forming an amorphous carbon mask covering the second region. The metal nitride layer exposed by the amorphous carbon mask may be etched, forming a preliminary metal nitride pattern. The amorphous carbon mask may be removed. A conductive layer may be formed on the surface of the substrate having the preliminary metal nitride pattern. The conductive layer and the preliminary metal nitride pattern may be etched, forming a first gate electrode in the first region and a second gate electrode in the second region. The first gate electrode may be a PMOS gate electrode and the second gate electrode may be a NMOS gate electrode, or vice versa.
The gate insulating layer may be a high-k dielectric layer. The high-k dielectric layer may be formed of a compound selected from the group consisting of HfO2, HfSiO, TiO2, Al2O3, Ta2O5 and ZrO2. The metal nitride layer may be a TaN layer or a TiN layer.
The amorphous carbon layer may be formed using a CVD process. The deposition process may be performed at a temperature of about 200° C. to 400° C. The amorphous carbon layer may be formed having a thickness of about 2000 Å to 5000 Å. The amorphous carbon mask may be removed using an ashing process.
After forming the first gate electrode and the second gate electrode, source/drain regions may be formed in the substrate at sides of the first gate electrode and the second gate electrode, respectively. After forming the amorphous carbon mask, nitrogen impurities may be implanted into the metal nitride layer exposed by the amorphous carbon mask.
Example embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Various example embodiments of the present invention will now be described more fully with reference to the accompanying drawings in which some example embodiments of the invention are shown. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.
Detailed illustrative embodiments of the present invention are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments of the present invention. This invention may, however, may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
Accordingly, while example embodiments of the invention are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments of the invention to the particular forms disclosed, but on the contrary, example embodiments of the invention are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of example embodiments of the present invention.
Spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or a feature's relationship to another element or feature as illustrated in the Figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation which is above as well as below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.
Also, the use of the words “compound,” “compounds,” or “compound(s),” refer to either a single compound or to a plurality of compounds. These words are used to denote one or more compounds but may also just indicate a single compound.
Example embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, example embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but may include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient (e.g., of implant concentration) at its edges rather than an abrupt change from an implanted region to a non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation may take place. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope of the present invention.
It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the FIGS. For example, two FIGS. shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments of the present invention belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In order to more specifically describe example embodiments of the present invention, various aspects of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited to the example embodiments described.
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A photosensitive layer pattern 67 may be formed on the substrate having the mask layer 63 to cover the PMOS region P of the peripheral region II. The photosensitive layer pattern 67 may expose the cell region I and the NMOS region N of the peripheral region II. An anti-reflective coating layer 65 may be interposed between the mask layer 63 and the photosensitive layer pattern 67. The anti-reflective coating layer 65 may be a SiON layer. The anti-reflective coating layer 65 may be formed having a thickness of about 500 Å.
Although not shown in the drawing, prior to forming the gate insulating layer 59, N-type or P-type impurities may be selectively implanted into the substrate having the wells in order to control a threshold voltage of a transistor. The implanted impurities may be activated by a thermal treatment process.
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Example embodiments of the present invention are also applicable to forming the cell gate electrode with a recessed shape.
According to example embodiments of the present invention, because the mask layer for etching the metal nitride layer may be formed using a low temperature process, characteristics of the metal nitride layer may not be affected. The metal nitride layer may be more easily etching during a subsequent process.
According to other example embodiments of the present invention, because the mask may be removed using an ashing process, damage on the surface of the high-k dielectric layer, during the removal of the mask, may decrease.
The foregoing is illustrative of the example embodiments of the present invention and is not to be construed as limiting thereof. Although a few example embodiments of the present invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function, and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The present invention is defined by the following claims, with equivalents of the claims to be included therein. What is claimed is:
Number | Date | Country | Kind |
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10-2006-0005554 | Jan 2006 | KR | national |