Patent Application
20150287632
This application claims the priority of Chinese patent application number 201410136618.0, filed on Apr. 4, 2014, the entire contents of which are incorporated herein by reference.
The present invention relates generally to semiconductor device fabrication, and in particular, to a method of fabricating a semiconductor device and a method of fabricating a stacked chip.
With the development of multimedia technology, digital still cameras, digital video cameras and mobile phones with camera functions have gained increasing popularity among consumers. In addition to their pursuit for the miniaturization of these devices, customers are also demanding for an increasing improvement in the quality (i.e., clarity) of images captured by such devices. On the other hand, whether such a device could capture a high imaging quality heavily depends on what components the device incorporates. In particular, the imaging quality of a camera is determined by an incorporated imaging sensor, which is a critical component of the camera.
Nowadays, complementary metal-oxide-semiconductor (CMOS) image sensors adopting a stacked structure, thus referred to as stacked CMOS image sensors, are getting a greater share in the camera sensor market. Each of such stacked sensors is accomplished by a device chip (with pixels) and a logic chip (with circuitry) that is stacked and electrically interconnected with the device chip. Such architecture enables the stacked sensor to provide a great number of pixels while keeping a relatively small size. Additionally, dispersing the pixel and circuitry parts on different chips allows the parts to be optimized separately for a higher imaging quality and a higher performance, respectively. As a result, compared to conventional backside-illuminated (BSI) sensors, stacked sensors are typically smaller in size while having higher performance.
However, a problem associated with the stacked sensors is that the existing processes for their fabrication are generally complex (e.g., the formation of mask patterns involves the use of many masks), costly and low in throughput.
It is therefore an objective of the present invention to provide a method of fabricating a semiconductor device and a method of fabricating a stacked chip, both capable of simplifying semiconductor fabrication processes (e.g., the fabrication processes of stacked sensors), increasing the throughput of a semiconductor fabrication plant (FAB) and reducing fabrication cost.
In accordance with the above and further objectives of the invention, a method of fabricating a semiconductor device includes: providing a substrate having a device function layer formed thereon; forming a first opening in the device function layer, the first opening extending through the device function layer, the first opening having a side-to-bottom angle of smaller than 90°; and etching the substrate to form therein a second opening by using the device function layer as a mask and the first opening as a mask pattern.
Optionally, the method may further include forming a first barrier layer on the device function layer, prior to forming the first opening in the device function layer.
Further, the first barrier layer may be formed of an oxide, a nitride or a carbide.
Further, the first barrier layer may have a thickness of 10 Å to 1000 Å.
Optionally, the method may further include forming a second barrier layer on the device function layer, after forming the first opening and prior to forming the second opening.
Further, the second barrier layer may be formed of an oxide, a nitride or a carbide.
Further, the second barrier layer may have a thickness of 10 Å to 5000 Å.
Further, the second barrier layer may have a non-conformal step coverage region in the first opening.
In another aspect, the present invention provides a method of fabricating a stacked chip, including: providing a first chip and a second chip, the first chip including a first substrate and a first epitaxial layer formed on the first substrate, the first epitaxial layer including a first interconnect structure, the second chip including a second substrate and a second epitaxial layer formed on the second substrate; stacking the first and second chips, with a side of the first epitaxial layer opposite the first substrate brought in contact with a side of the second epitaxial layer opposite the second substrate; forming a first opening in the first substrate, the first opening extending through the first substrate, the first opening having a side-to-bottom angle of smaller than 90°; and etching the first epitaxial layer to form therein a second opening by using the first substrate as a mask and the first opening as a mask pattern, the second opening exposing the first interconnect structure.
Further, the first interconnect structure may include a first cap metal layer and at least one metal interconnect layer, the first cap metal layer stacked with the at least one metal interconnect layer. Additionally, the first cap metal layer may be located on a side of the at least one metal interconnect layer opposite the first substrate, and the second opening may expose one of the at least one metal interconnect layer closest to the first substrate.
Further, the second epitaxial layer may include a second interconnect structure, and the method may further include forming, within the first opening, a third opening exposing the second interconnect structure.
Further, the third opening may be within the second opening.
Further, the second and third openings may be formed by an all-in-one etching process.
Further, the first epitaxial layer may include an interconnect region and an opening region. In addition, the first interconnect structure may be disposed in the interconnect region, and the third opening may be disposed in the opening region.
Further, the second interconnect structure may include a second cap metal layer, and the third opening may expose the second cap metal layer.
Optionally, the method may further include filling the first and second openings with a conductive layer.
Optionally, the method may further include forming a first barrier layer on a side of the first substrate opposite the first epitaxial layer, prior to forming the first opening.
Further, the first barrier layer may be formed of an oxide, a nitride or a carbide.
Further, the first barrier layer may have a thickness of 10 Å to 1000 Å.
Optionally, the method may further include forming a second barrier layer on the side of the first substrate opposite the first epitaxial layer, after forming the first opening in the first substrate and prior to forming the second opening in the first epitaxial layer.
Further, the second barrier layer may be formed of an oxide, a nitride or a carbide.
Further, the second barrier layer may have a thickness of 10 Å to 5000 Å.
Further, the second barrier layer may have a non-conformal step coverage region in the first opening.
The methods of the present invention provide the following advantages over the prior art.
First, in the fabrication of the semiconductor device according to the present invention, with the first opening having a side-to-bottom angle of smaller than 90° (i.e., broader at the bottom and narrower at the top) serving as a mask pattern for the subsequent etching step of forming the second opening in the substrate, the formed second opening gains a size equal to the top-edge size of the first opening. This circumvents the necessity of preparing a separate mask for forming the second opening, thus resulting in process simplification, enhanced productivity and cost reduction.
Secondly, by forming the first and second openings of a stacked chip in the same manner as the above-mentioned fabrication method of the semiconductor device, the forming method of the present invention can achieve all the same benefits, i.e., a simplified process, enhanced productivity and reduced cost.
The methods of the present invention will be described in greater detail in the following description which demonstrates preferred embodiments of the present invention, in conjunction with the accompanying drawings. Those of skill in the art should, in light of the present disclosure, appreciate that many changes can be made in the specific embodiments disclosed herein and still obtain the same beneficial results. Therefore, the following description should be construed as the illustrative of the principles of the present invention, and not providing limitations thereto.
For simplicity and clarity of illustration, not all features of the specific embodiments are described. Additionally, descriptions and details of well-known functions and structures are omitted to avoid unnecessarily obscuring the invention. The development of any specific embodiment of the present invention includes specific decisions made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, such a development effort might be complex and time consuming but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The present invention will be further described in the following paragraphs by way of example with reference to the accompanying drawings. Features and advantages of the present invention will be apparent from the following detailed description, and from the appended claims. Note that the accompanying drawings are provided in a very simplified form not necessarily presented to scale, with the only intention of facilitating convenience and clarity in explaining a few exemplary embodiments of the present invention.
In accordance with the principles of the present invention, a method of fabricating a semiconductor device is provided, including the steps of:
step S11: providing a substrate having a device function layer formed thereon;
step S12: forming a first opening in the device function layer, the first opening extending through the device function layer, the first opening having a side-to-bottom angle of smaller than 90°; and
step S13: etching the substrate to form therein a second opening by using the device function layer as a mask and the first opening as a mask pattern.
Advantageously, with the first opening having a side-to-bottom angle of smaller than 90° (i.e., broader at the bottom and narrower at the top) serving as a mask pattern for the subsequent etching step for forming the second opening in the substrate, the formed second opening gains a size that is equal to the top-edge size of the first opening. This circumvents the necessity of preparing a separate mask for forming the second opening, thus resulting in process simplification, enhanced productivity and cost reduction.
In accordance with the principles of the present invention, a method of fabricating a stacked chip is also provided. In this method, a first opening and a second opening are formed in the same manner as the above-described fabricating method, and all the same benefits, i.e., a simplified process, enhanced productivity and reduced cost, are thus achievable. The fabricating method includes the steps of:
step S21: providing a first chip and a second chip, the first chip including a first substrate and a first epitaxial layer formed on the first substrate, the first epitaxial layer including a first interconnect structure, the second chip including a second substrate and a second epitaxial layer formed on the second substrate, the first chip and the second chip being stacked together with a side of the first epitaxial layer opposite the first substrate brought in contact with a side of the second epitaxial layer opposite the second substrate;
step S22: forming a first opening in the first substrate, the first opening extending through the first substrate, the first opening having a side-to-bottom angle of smaller than 90°; and
step S23: etching the first epitaxial layer to form therein a second opening that exposes the first interconnect structure by using the first substrate as a mask and the first opening as a mask pattern.
The present invention will become more apparent from the detailed description of several exemplary embodiments set forth below. It is to be understood that this invention is not limited to these embodiments, and modifications made thereto by those of ordinary skill in the art based on common technical means are also considered to be within the scope of the invention.
A method of fabricating a semiconductor device in accordance with this embodiment is described by referencing
Turning now to
Preferably, as shown in
Referring to
In this embodiment, a second barrier layer 140 is further formed over the device function layer 120 before the next step S13 and after step S12. In this process, as shown in
In the step S13, as shown in
A method of fabricating a stacked chip in accordance with this embodiment is described by referencing
Reference is first made to
With continuing reference to
The first epitaxial layer 220 may further include a first protective layer 223, a first dielectric layer 224 and other like features. The first protective layer 223 may be formed on a side of a first cap metal layer 2TM opposite the first substrate 210 so as to act as a protection layer of the first cap metal layer 2TM. First interconnect structure 221 may be disposed within the first dielectric layer 224 so as to be electrically insulated. As illustrated, the first epitaxial layer 220 has an interconnect region 220b and an opening region 220a, and the first interconnect structure 221 is formed in the interconnect region 220b.
In this embodiment, the first interconnect structure 221 includes a first metal interconnect layer 2M1, a second metal interconnect layer 2M2, a third metal interconnect layer 2M3 and aforementioned first cap metal layer 2TM. The first, second and third metal interconnect layers 2M1, 2M2 and 2M3 and the first cap metal layer 2TM are stacked together in this order, with the first cap metal layer 2TM disposed on a side of the third metal interconnect layer 2M3 opposite the first substrate 210. In alternative embodiments, the first interconnect structure 221 may only include the third metal interconnect layer 2M3 and the first cap metal layer 2TM, or only include the first cap metal layer 2TM, and both are considered within the scope of the invention. Further, while three metal interconnect layers (i.e., the first metal interconnect layer 2M1, the second metal interconnect layer 2M2 and the third metal interconnect layer 2M3) are illustrated, it will be appreciated by those skilled in the art that the invention is not limited in this regards as first interconnect structure 221 may also include four or more metal interconnect layers.
Preferably, the second epitaxial layer 320 includes a second interconnect structure 322. In this embodiment, the second interconnect structure 322 is implemented as a second cap metal layer. In alternative embodiments, the second interconnect structure 322 may further include several metal interconnect layers, or have a structure designed to meet practical requirements. Similarly, the second epitaxial layer 320 may further include a second protective layer 323, a second dielectric layer 321 and other like features. Second protective layer 323 may reside on a side of the second interconnect structure 322 opposite the second substrate 310 so as to protect the second interconnect structure 322, and the second interconnect structure 322 may be disposed within the second dielectric layer 321 for electrical insulation.
Preferably, as shown in
Referring to
In this embodiment, a second barrier layer 240 is further formed over the side of the first substrate 210 opposite the first epitaxial layer 220 before a subsequent step S24 and after step S23. In this process, as shown in
Considering there are further two openings, a third opening for exposing the second interconnect structure 322 and a second opening, to be subsequently formed in this embodiment, it is desirable to form these two openings by an all-in-one (AIO) etching process. Although the following description is made in the context of the second and third openings to be formed using an AIO etching process, it should be appreciated that the invention is not limited in this regards as the second and third openings can also be formed in separate processes.
Referring to
Afterward, in the fourth step S24, as shown in
In addition, the etching process of this step is an AIO etching process, wherein during the first epitaxial layer 220 is being etched to form the second opening 282, the third opening 283 is concurrently deepened and finally penetrates through the first epitaxial layer 220, exposing the second interconnect structure 322. For the sake of chip area saving, third opening 283 is preferably formed within the second opening 282.
Moreover, since the first interconnect structure 221 includes the first metal interconnect layer 2M1, the second metal interconnect layer 2M2, the third metal interconnect layer 2M3 and the first cap metal layer 2TM, the etching process may be stopped upon the first metal interconnect layer 2M1 being exposed in the second opening 282 (the one closest to first substrate 210 among the four layers of the interconnect structure 221). This is advantageous to preventing the second opening 282 from having an unnecessarily large depth to save materials, energy and time consumed in the etching process.
After step S24, a conductive layer 250 may be further formed, filling each of the first opening 28, the second opening 282 and the third opening 283, as shown in
In this embodiment, the first and second chips 200, 300 are implemented as a device chip and a logic chip, respectively, such that the formed stacked chip functions as a stacked sensor. It shall be appreciated, however, that it is within the scope of the present invention for the first and second chips 200, 300 to be chips of other functions.
In conclusion, the methods of the present invention provide the following advantages over the prior art.
First, in the method of fabricating a semiconductor device of the invention, with the first opening having a side-to-bottom angle of smaller than 90° (i.e., broader at the bottom and narrower at the top) serving as a mask pattern for the subsequent etching step of forming the second opening in the substrate, the formed second opening gains a size equal to the top-edge size of the first opening. This circumvents the necessity of preparing a separate mask for forming the second opening, thus resulting in process simplification, enhanced productivity and cost reduction.
Secondly, by forming the first and second openings in the same manner as the foregoing fabricating method, the method of forming a stacked chip of the present invention can achieve all the same benefits, i.e., a simplified process, enhanced productivity and reduced cost.
Obviously, those skilled in the art may make various modifications and alterations without departing from the spirit and scope of the invention. It is therefore intended that the present invention be construed as including all such modifications and alterations insofar as they fall within the scope of the appended claims or equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201410136618.0 | Apr 2014 | CN | national |
