Higher memory density is always in demand to provide smaller devices with increased memory capacity. Forming memory devices laterally on a surface of a semiconductor chip uses a great deal of chip real estate. Improved memory devices are needed with new configurations to further increase memory density beyond what is available with traditional devices.
In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which are shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and logical, electrical, material changes, etc. may be made.
The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a substrate, such as a wafer or die, regardless of the orientation of the substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the substrate, regardless of the orientation of the substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
An opening 110 having a sidewall 112 is shown in the substrate 100.
The diffusion mechanism of the n-type dopant into the semiconductor material 104 provides a number of useful features with respect to the diffused regions 106 and the opening 110. Diffusion distance into the semiconductor portion 104 is substantially dependent on time, temperature, and concentration of a dopant source. Diffusion distance into the semiconductor material 104 is not substantially affected by aspect ratio or depth of the opening 110. As a result, the diffused regions 106 extend a substantially identical distance into the semiconductor material 104 at the top 116 and the bottom 118 of the opening 110. Although diffusion of an n-type dopant is used as an example, other dopants, such as p-type dopants, that provide etching selectivity are also within the scope of the invention.
In one example, phosphorous is used as the n-type dopant. One example of phosphorous diffusion includes furnace processing using phosphine as a phosphorous source. Another example of phosphorous diffusion includes furnace processing using POCl3 gas as a phosphorous source. Another example of phosphorous diffusion includes deposition of a phosphorous doped material on an exposed surface of the semiconductor material 104, and a subsequent anneal to drive the phosphorous into the semiconductor material 104. Example materials to provide dopants to diffuse into the exposed surface of the semiconductor material 104 include phosphorous doped polysilicon, or phospho-silicate glass. Examples of deposition include chemical vapor deposition and pulsed laser ablation deposition.
Attempting to etch a same doped semiconductor material 104 by itself presents a number of technical challenges. P+ doped silicon, for example, is difficult to etch at an appreciable rate using wet etch chemistries based on hydroxides. HF—HNO3 based chemistries can etch p+ doped silicon, however HF—HNO3 based chemistries are not sufficiently selective with respect to dielectrics such as silicon oxide. Plasma etch is sensitive to aspect ratio, such that a layer of material at the bottom 118 of the opening 110 may etch more slowly than a layer of material at the top 116 of the opening 110.
In the processes of an embodiment of the present invention, diffusion of n-type dopants into the semiconductor material 104 is substantially insensitive to aspect ratio or depth within the opening 110. Subsequent etchant chemistries, such as the example hydroxyl chemistries listed above, are available that are selective between n-type and p-type silicon, and selective with respect to dielectrics such as silicon oxide. As a result, the recesses 120 formed are substantially consistent in their distance into the semiconductor material 104 from a sidewall 112 of the opening 110 from the top 116 to the bottom 118 of the opening 110.
As discussed above, memory devices are one type of semiconductor device that may be formed using the etching processes described.
In one example, the elongated channel region 210 comprises n type semiconductor material, such as n-type polysilicon. A source region 230 and a drain region 232 are shown coupled to a first end 211 and a second end 213 of the elongated channel region 210, respectively. In one example, the source region 230 and the drain region comprises p type semiconductor material, such as p-polysilicon. In operation, the pathway of source region 230, to elongated channel region 210, to drain region 232 acts as a p-n-p transistor, with select gates 220, 222, and memory cell gates 214 operating to allow, or inhibit signal transmission along the way. In the example shown, the source region 230, elongated channel region 210, drain region 232, select gates 220, 222, and memory cell gates 214 collectively form a memory cell string 201. In the example shown in
A source line 226 and a data line, such as bitline 228, are shown coupled to the source region 230 and the drain region 232 respectively. In one embodiment, a plug 224 is used to couple the bitline 228 to the drain region 232. Each of the source line 226, bitline 228 and plug 224 can comprise, consist of, or consist essentially of metal, such as aluminum, copper, or tungsten, or alloys of these or other conductor metals. As used herein, the term “metal” further includes metal nitrides, or other materials that operate primarily as conductors.
In one specific example using TMAH, testing provided the following etch rate results.
The table confirms that heavily doped boron (for example 1×1021 atoms/cm3 in the table) has a dramatic fall in etch rate.
An embodiment of an information handling system such as a computer is included in
In this example, information handling system 400 comprises a data processing system that includes a system bus 402 to couple the various components of the system. System bus 402 provides communications links among the various components of the information handling system 400 and may be implemented as a single bus, as a combination of busses, or in any other suitable manner.
Chip assembly 404 is coupled to the system bus 402. Chip assembly 404 may include any circuit or operably compatible combination of circuits. In one embodiment, chip assembly 404 includes a processor 406 that can be of any type. As used herein, “processor” means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit.
In one embodiment, a memory device 407 is included in the chip assembly 404. In one embodiment, the memory device 407 includes a NAND memory device formed according to embodiments described above. In one embodiment, the processor 406 and memory device 407 are formed on the same chip.
In one embodiment, additional logic chips 408 other than processor chips are included in the chip assembly 404. An example of a logic chip 408 other than a processor includes an analog to digital converter. Other circuits on logic chips 408 such as custom circuits, an application-specific integrated circuit (ASIC), etc. are also included in one embodiment of the invention.
Information handling system 400 may also include an external memory 411, which in turn can include one or more memory elements suitable to the particular application, such as one or more hard drives 412, and/or one or more drives that handle removable media 413 such as compact disks (CDs), flash drives, digital video disks (DVDs), and the like. A semiconductor memory die constructed as described in examples above is included in the information handling system 400.
Information handling system 400 may also include a display device 409 such as a monitor, additional peripheral components 410, such as speakers, etc. and a keyboard and/or controller 414, which can include a mouse, touch sensor, voice-recognition device, or any other user interface device that permits a system user to input information into and receive information from the information handling system 400.
While a number of embodiments of the invention are described, the above lists are not intended to be exhaustive. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon studying the above description.
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Number | Date | Country | |
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20130040429 A1 | Feb 2013 | US |