Patent Application
20150181724
The present disclosure relates to printed circuit boards (PCBs), and more particularly, to methods of forming segmented vias in a printed circuit board (PCB).
Consumers are increasingly demanding both faster and smaller electronic products. The use of PCBs has grown enormously as new electronic applications are marketed. A PCB is formed by laminating a plurality of conducting layers with one or more non-conducting layers. As the size of a PCB shrinks, the relative complexity of its electrical interconnections grows.
A via structure is traditionally used to allow signals to travel between layers of a PCB. The plated via structure is a plated hole within the PCB that acts as a medium for the transmission of an electrical signal. For example, an electrical signal may travel through a trace on one layer of the PCB, through the plated via structure's conductive material, and then into a second trace on a different layer of the PCB.
The via 130 allows an electrical signal 160 to transmit from one trace 140 or component mounting pad on a first conducting layer 110a to another trace 150 on a second conducting layer 110b of the PCB 100 by traversing the isolated portion 130a of the via 130. Similarly, the isolated portion 130b of the via 130 allows another electrical signal 162 to transmit to a trace 180 without interfering with the signal 160.
The plating resist 170 limits the deposition of, or deactivates, the catalyzing material 190 and prevents conductive material 192 within the via structure 130 at the conducting layer 110d. As a result, the via 130 is partitioned into the electrically isolated portions 130a, and 130b. Consequently, the electric signal 160 travels from the first conducting layer 110a to the second conducting layer 110c without signal integrity being degraded through interference caused by electrically isolated portion 130b.
Optionally, a second core or sub-composite structure, having a second dielectric core layer sandwiched between a third conductive layer and a fourth conductive layer, is formed 208. At least one conductive layer of the second core or sub-composite structure may be etched to form via pads, antipads, and/or electrical traces 210. For instance, such etching may serve to form electrical paths to/from points where vias are to be formed. A second plating resist material may then be deposited on at least one surface of the second core or sub-composite structure 212.
The first core or sub-composite structure and second core or sub-composite structure may then be laminated with at least one dielectric layer in between, forming a PCB stackup 214. Through holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist 216. Next, a seeding conductive material, such as electroless copper plating, is applied to the one or more through holes 218.
Electrolytic plating is applied to the one or more through holes 220. Then the outer layer circuit or signal traces are then formed 222. That is, the etching of paths on the conductive foils/layers of the core structure.
The electroless copper provides the initial conductivity path to allow for additional electrolytic copper plating of the barrel of each through hole in the stackup. The seed chemistry (catalyst) deposits on the surface of the through hole wall and although the plating resist is designed to prevent copper deposition on the plating resist, some of the catalyst may still be deposited on the plating resist. Catalyst remaining on the surface of the through hole after plating can result in poor insulation (high resistance short, electromigration) and burly plating. Consequently, there is a need for improved methods for removing the catalyst after the plating process when forming a segmented via in a printed circuit board.
The following presents a simplified summary of one or more implementations in order to provide a basic understanding of some implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.
According to one feature, a method for making a printed circuit board having a segmented plated through hole is provided. The method includes forming a core or sub-composite structure; selectively depositing at least one plating resist on a dielectric layer within the core or sub-composite structure or external to the core or sub-composite structure; forming one or more through holes through the core or sub-composite structure and the plating resist; and applying a catalyzing material to an interior surface of the one or more through holes, the interior surface having a laminate portion and a plating resist portion where only the laminate portion is coated with a conductive material; applying electroless plating to the one or more through holes; removing the catalyzing material from the plating resist portion using a catalyst remover; applying electrolytic plating to the one or more through holes; and forming an outer layer circuit on the external conductive layers.
According to one aspect, the catalyzing material is palladium or a palladium derivative and the catalyst remover is an acidic solution and wherein the acidic solution includes at least nitrite or nitrite ion and halogen ion.
According to another one aspect, the catalyst remover is an etchant for plating resist and the etchant is an alkaline permanganate compound solution. The etchant may be plasma gas wherein the plasma gas includes at least one of oxygen, nitrogen, argon and tetrafluoromethane.
According to another feature, a method for making a printed circuit board having a segmented plated through hole is provided. The method includes forming a core or subcomposite structure; selectively depositing at least one plating resist on a dielectric layer within the core or sub-composite structure or external to the core or sub-composite structure; forming a through hole through the core or sub-composite structure and the plating resist; applying a catalyzing material to an interior surface of the one or more through holes, the interior surface having a laminate portion and a plating resist portion where only the laminate surface is to be coated with a conductive material applying metal plating to the one or more through holes; removing the catalyzing material from the plating resist portion using a catalyst remover; and forming an outer layer circuit on the conductive layers of the first core.
According to one aspect, the catalyzing material is palladium or a palladium derivate.
According to another aspect, the catalyst remover is an acidic solution and wherein the acidic solution includes at least nitrite or nitrite ion and halogen ion.
According to yet another aspect, the catalyst remover is an etchant for plating resist.
According to yet another aspect, the etchant is an alkaline permanganate compound solution.
According to yet another aspect, the etchant is plasma gas and wherein the plasma gas includes at least one of oxygen, nitrogen, argon and tetrafluoromethane.
According to yet another feature, a method for making a printed circuit board having a segmented plated through hole is provided. The method includes forming a core or subcomposite structure; selectively depositing at least one plating resist on a dielectric layer within the core or sub-composite structure or external to the core or sub-composite structure; forming a through hole through the core or sub-composite structure and the plating resist; and applying a catalyzing material to an interior surface of the one or more through holes, the interior surface having a laminate portion and a plating resist portion where the laminate surface is to be coated with a conductive material and the plating resist portion is not to be plated with a conductive material; applying metal plating to the one or more through holes; forming an outer layer circuit on the conductive layers of the first core; and removing the catalyzing material from the plating resist portion and dielectric material surface using a catalyst remover.
According to one aspect, the catalyzing material is palladium or a palladium derivate.
According to another aspect, the catalyst remover is an acidic solution.
According to yet another aspect, the acidic solution includes at least nitrite or nitrite ion and halogen ion.
According to yet another aspect, the catalyst remover is an etchant for plating resist.
According to yet another aspect, the catalyst remover is an etchant for plating resist.
According to yet another aspect, the etchant is an alkaline permanganate compound solution.
In the following detailed description of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. However, the disclosure may be practiced without these specific details. In other instances, well known methods, procedures, and/or components have not been described in detail so as not to unnecessarily obscure aspects of the disclosure.
The present disclosure provides methods for forming segmented vias, or through holes, in multi-layer printed circuit board. A multilayer PCB can be a chip substrate, a motherboard, a backplane, a backpanel, a centerplane, a flex or rigid flex circuit. The present disclosure is not restricted to use in PCBs. A via structure can be a plated through hole (PTH) used for transmitting electrical signals from one conducting layer to another. A plated via structure can also be a component mounting hole for electrically connecting an electrical component to other electrical components on the PCB.
The present disclosure provides a method of making a printed circuit board which utilizes a novel catalyst removing process after the plating process. In one example of making the PCB, a core or sub-composite structure is formed and at least one plating resist material (or plating resist) may be selectively deposited on a dielectric layer within the core or sub-composite structure or external to the core or sub-composite structure. Next, one or more through holes are formed through the core or sub-composite structure and the plating resist; and a catalyzing material is applied to an interior surface of the one or more through holes, the interior surface having a laminate portion and a plating resist portion where only the laminate portion is coated with a conductive material. Electroless plating is then applied to the one or more through holes and the catalyzing material is removed from the plating resist portion using a catalyst remover. After removing the removing from the plating resist, electrolytic plating is applied to the one or more through holes and an outer layer circuit on the external conductive layers is formed.
When electroless copper plating is to be performed on through holes for formation of plated through holes or hole portions for formation of via holes, a catalyzing process is usually performed prior to electroless copper plating so as to deposit palladium (Pd), which serves as a plating initiator nucleus for deposition in electroless plating.
Optionally, a second core or sub-composite structure, having a second dielectric core layer sandwiched between a third conductive layer and a fourth conductive layer, may be formed 508. At least one conductive layer of the second core or sub-composite structure may be etched to form via pads, antipads, and/or electrical traces 510. For instance, such etching may serve to form electrical paths to/from points where vias are to be formed. A second plating resist material may then be deposited on at least one surface of the second core or sub-composite structure 512. The process of forming additional cores or sub-composite structures 508-512 may be repeated as necessary.
The first core or sub-composite structure, as well as any optionally additional corresponding composite structures, such as the second core or sub-composite structure, may then be laminated with at least one dielectric layer in between, forming a PCB stackup 514. One or more through holes may be drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist materials (or plating resist) 516. Next, a seeding conductive material or a catalyzing material for electroless copper plating, such as palladium catalyst, may be applied to the one or more through holes 518 and then electroless copper may be applied 520.
After the electroless plating, excess catalyst on the surface of the plating resist materials (or plating resist) may be removed 522. The catalyst may then be removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, electrolytic plating may then be applied to the one or more through holes 524. Next, the outer layer circuit or signal traces may then be formed on the external conductive layers 526. That is, the etching of paths on the conductive foils/layers of the core structure.
Optionally, a second core or sub-composite structure, having a second dielectric core layer sandwiched between a third conductive layer and a fourth conductive layer, may be formed 608. At least one conductive layer of the second core or sub-composite structure may be etched to form via pads, antipads, and/or electrical traces 610. For instance, such etching may serve to form electrical paths to/from points where vias are to be formed. A second plating resist material (or plating resist) may then be deposited on at least one surface of the second core or sub-composite structure 612. The process of forming additional cores or sub-composite structures 608-612 may be repeated as necessary.
The first core or sub-composite structure, as well as any optionally additional corresponding composite structures, such as the second core or sub-composite structure, may then be laminated with at least one dielectric layer in between, forming a PCB stackup 614. One or more through holes may be drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist materials (or plating resist) 616. Next, a seeding conductive material or catalyzing material for electroless copper plating, such as palladium catalyst, may be applied to the one or more through holes 618 and then electroless copper is applied 620.
Electrolytic plating may then be applied to the one or more through holes 622. After the electrolytic plating, excess catalyst on the surface of the plating resist may be removed 624. The catalyst may be removed using a catalyst cleaner or remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses. After removal of the excess catalyst, the outer layer circuit or signal traces may then be formed 626. That is, the etching of paths on the conductive foils/layers of the core structure. According to one embodiment, the catalyst cleaning process may be applied after circuit or trace formation instead of the catalyst cleaning before circuit or trace formation.
Optionally, a second core or sub-composite structure, having a second dielectric core layer sandwiched between a third conductive layer and a fourth conductive layer, may be formed 708. At least one conductive layer of the second core or sub-composite structure may be etched to form via pads, antipads, and/or electrical traces 710. For instance, such etching may serve to form electrical paths to/from points where vias are to be formed. A second plating resist material may then be deposited on at least one surface of the second core or sub-composite structure 712. The process of forming additional cores or sub-composite structures 708-712 may be repeated as necessary.
The first core or sub-composite structure, as well as any optionally additional corresponding composite structures, such as the second core or sub-composite structure, may then be laminated with at least one dielectric layer in between, forming a PCB stackup 714. Through holes may be drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist 716. Next, a seeding conductive material or catalyzing material for electroless copper plating, such as palladium catalyst, may be applied to the one or more through holes 618 and then electroless copper may be applied 720.
Electrolytic plating may then applied to the one or more through holes 720. After the electrolytic plating, excess catalyst on the surface of the plating resist may be removed 722. The outer layer circuit or signal traces may then be formed 724. That is, the etching of paths on the conductive foils/layers of the core structure. Finally, the catalyzing material may be removed using a catalyst remover, such as an acidic solution that includes at least nitrite or nitrite ion and halogen ion, or the catalyst remover may be an etchant for plating resist, such as alkaline permanganate compound solution or plasma gas comprising at least one of oxygen, nitrogen, argon and tetrafluoromethane, or a mixture of at least two of these gasses.
Cross-Sectional View of Through-Hole with Residual Catalyst Deactivated
As shown in
A second set of catalyst particles (or catalyst) 1010 located on the plating resist portion 1004 can be deactivated 1012. Although these catalyst particles (or catalyst) 1010 can be deactivated or made inert, there is still catalyst that remains on the surface after plating which could cause poor insulation (high potential, migration) and burly plating.
Cross-Sectional View of Through-Hole with Residual Catalyst Removed
As shown in
The second set of catalyst particles (or catalyst) 1010 shown in
In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The invention is intended to be as broad as the appended claims, including all equivalents thereto.
Those skilled in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.
While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art.
The present Application for Patent claims priority to U.S. Provisional Application No. 61/917,262 entitled “Methods of Forming Segmented Vias for Printed Circuit Boards”, filed Dec. 17, 2013, which is hereby expressly incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61917262 | Dec 2013 | US |
