The present disclosure relates to semiconductors and, more particularly, to methods of manufacturing metal oxide semiconductor field effect transistors (MOSFETS) in semiconductor devices.
In general, a MOSFET has a structure including a gate electrode, a source/drain electrode, and an oxide layer therebetween, which are formed on a silicon substrate.
Recently, as semiconductor devices have become highly integrated, miniaturized, and lightweight, physical size of the MOSFET is scaled down, thereby decreasing a valid channel length and causing a short channel effect deteriorating a punch-through between a source and a drain.
To resolve such problems, a source/drain formed in a lightly doped drain (hereinafter referred to as “LDD”) structure have been proposed. The source/drain has a shallow junction to decrease the short channel effect. However, in a highly integrated semiconductor device having a MOSFET with a smaller line width, it is difficult to fabricate the LDD structure.
Meanwhile, U.S. Pat. No. 6,521,508 discloses a method for manufacturing a contact plug in a semiconductor device using a selective epitaxial silicon growth process, and U.S. Pat. No. 5,633,201 discloses a method for forming tungsten (or aluminum) plugs in contact holes of highly integrated semiconductor device. However, as a semiconductor device becomes highly integrated and,miniaturized, contacts connected with the gate electrode, a bit line and contact holes therefore are getting smaller. Accordingly, a contact hole manufacturing process for forming the contacts or contact plugs by depositing a conductive material into the contact holes comes to have limitations when the contact holes are formed in the highly integrated semiconductor device.
Referring to
Subsequently, a silicon oxide layer as a gate dielectric layer 14 is formed on the epitaxial active region 11. A doped polysilicon layer is deposited on the gate dielectric layer 14 and a gate electrode 16 is formed by patterning the doped polysilicon layer. A spacer dielectric layer 18 is formed on sidewalls of the gate electrode 16.
As shown in
According to one example, the source/drain plug 22a, 22b is formed of a n+/p+ doped silicon layer, a source/drain 23a, 23b is formed by diffusing a n+/p+ dopant into the epitaxial active region 11 using an annealing process.
Alternatively, according to another example, the source/drain plug 22a, 22b is formed of an undoped silicon layer, the source/drain 23a, 23b is formed by diffusing the n+/p+ dopant into the epitaxial active region 11 by practicing a doped ion implantation process and an annealing process, sequentially.
The spacer dielectric layer 18 and the gate dielectric layer 14 thereunder are then removed.
As a result, the gate electrode 16 and the source/drain plug 22a, 22b are separated by a gap 20 equal to the thickness of the spacer dielectric layer 18, and the gap 20 will be a length of an LDD region, as described hereinafter.
Referring to
As shown in
Conversely, the LDD region may be formed by using the interlayer dielectric layer 26 made of a borosilicate glass (“BSG”) or a phosphosilicate glass (“PSG”) instead of the ion implantation process described above. Specifically, after the spacer dielectric layer 18 and the gate dielectric layer thereunder are removed, the interlayer dielectric layer 26 made of the BSG or the PSG is formed on the entire surface of the resultant structure. The LDD region 24 is then formed by diffusing B (p dopant) or P (n dopant) of the interlayer dielectric layer 26 into the epitaxial active region 11 between the gate electrode 16 and the source/drain plug 22a, 22b using the annealing process.
In accordance with the process of the present invention, the active region and the source/drain plug are formed by performing a selective epitaxial silicon growth process. As a result, a short channel effect of the highly integrated semiconductor devices can be prevented and a contact hole manufacturing process for forming the source/drain plug can be eliminated.
Although certain methods are described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers every apparatus, method and article of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.
Number | Date | Country | Kind |
---|---|---|---|
10-2002-0086240 | Dec 2002 | KR | national |
Number | Name | Date | Kind |
---|---|---|---|
5633201 | Choi | May 1997 | A |
6462366 | Hsu et al. | Oct 2002 | B1 |
6521508 | Cheong et al. | Feb 2003 | B1 |
6717202 | Sugawara et al. | Apr 2004 | B1 |
20010019872 | Havemann | Sep 2001 | A1 |
20020192868 | Kim | Dec 2002 | A1 |
Number | Date | Country | |
---|---|---|---|
20040137675 A1 | Jul 2004 | US |