Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation

Abstract

Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

Description

BACKGROUND

A central processor unit (CPU) also referred to as a processor, is the hardware within a computer that carries out the instructions of a computer program by performing the basic arithmetical, logical, and input/output operations of the system. Conventional processors can have a variety of architecture features that can include but are not limited to wide architectures, pipelined architectures and emulated architectures.

Processors that have wide architectures are capable of fetching and decoding multiple cache lines of instructions in parallel. In order to optimally support such wide architectures the processor frontend must be capable of supplying multiple cache lines of instructions to the processor scheduler and execution units during each clock cycle.

Processors that feature emulation allow software applications and operating systems written for other computer processor architectures to be run on the processors. Such processors have the capacity to duplicate (or emulate) the functions of another computer system (the guest architecture) such that the behavior emulated by the processors closely resembles the behavior of the other computer system (the guest architecture).

In emulated architectures, both native and guest branch (instructions) can be encountered. Native-branch instructions are branch instructions whose target is an address in the native-space. Guest-branch instructions are branch instructions whose target is an address in guest-space. Accordingly, a hardware structure such as a conversion-lookaside-buffer (CLB) is required to maintain the mapping of guest-to-native addresses.

In addition to native and guest branches, processors can encounter a variety of branch instruction types that can present challenges as regards supplying multiple cache-lines of instructions to the processors' scheduler and execution units during each clock cycle (because of complex program control flows). Such instructions can include what are termed “far branch” instructions and “near branch” instructions (e.g., loop instructions). Far branch instructions are instructions that can alter the flow of instruction execution in a program wherein instruction execution jumps outside of a cache line. Loop instructions are instructions that include a sequence of statements that are specified only once but that are carried out several times in succession before the loop is exited (and can involve jumps within a cache line).

In pipelined architectures multiple sequential instructions are executed simultaneously. However, the pipeline can only be fully utilized if the processor is able to read a next instruction from memory on every cycle. Importantly, the processor must know which instruction is to be next read in order to read that instruction. However, when a far branch instruction is encountered, the processor may not know ahead of time the path that will be taken and thus which instruction is to be next read. In such instances, the processor has to stall until this issue can be resolved. This process can degrade utilization and negatively impact processor performance.

Additionally, in some conventional processors, when a loop is encountered, instructions of the loop that are required to be repeated in successive iterations of the loop may need to be accessed in different clock cycles. This requirement can limit the number of instructions that can be forwarded per cycle. Accordingly, such processors can exhibit unsatisfactory latencies attributable to the delays in reading instructions from memory.

SUMMARY

In some conventional processors when a conditional branch instruction is encountered, it may not be known ahead of time which path will be taken and thus which instruction is to be read. In such instances, the CPU has to stall until the decision is resolved. This can degrade utilization and negatively impact processor performance. Additionally, in some conventional processors when a loop is encountered, the number of instructions that can be forwarded per cycle can be limited. Accordingly, such systems can exhibit unsatisfactory latencies that are attributable to delays in reading instructions from memory. Methods for a wide and efficient front-end operation with guest architecture emulation are disclosed that addresses these shortcomings. However, the claimed embodiments are not limited to implementations that address any or all of the aforementioned shortcomings. As a part of a method for wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a first cache line that includes the first far taken branch instruction, a next cache line and a cache line that is located at the target of the first far taken branch instruction is read. Based on information accessed from a data table, the first cache line and either the next cache line or the cache line at the target is fetched in a single cycle.

In the same or another embodiment, as a part of a method for wide and efficient front-end operation, (a) responsive to a request to fetch an instruction, it is determined if an instruction is to be successively accessed as a part of a loop; if the instruction is to be successively accessed, (b) a first cache line comprising the instruction is duplicated to provide a duplicated cache line, and the first cache line and the duplicated cache line are forwarded; (c) then it is determined if an instruction of the duplicated cache line has characteristics that correspond to a stored instruction tag that identifies an exit branch associated with the loop; (d) if the instruction of the duplicated cache line has characteristics that correspond to the stored instruction tag that identifies the exit branch, the loop is exited, and if the instruction of the duplicated cache line does not have characteristics that correspond to the stored instruction tag that identifies the exit branch return to (b). Based on the aforementioned operations, exemplary embodiments facilitate the maintenance of efficient processor frontend supply of multiple cache lines of instructions to the processor scheduler and execution units during each clock cycle, even where first far taken branches and loops are encountered.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:

FIG. 1A shows an exemplary operating environment of a system for supporting wide and efficient front-end operation with guest-architecture emulation according to one embodiment.

FIG. 1B shows an instruction cache and a shadow cache that stores a copy of a cache line that is copied from a target of a first far taken branch instruction according to one embodiment.

FIG. 1C shows an exemplary first far taken branch data table (FFTB DT) according to one embodiment.

FIG. 1D illustrates a reading of a first cache line which contains a first far taken branch, a next cache line and a target cache line according to one embodiment.

FIG. 1E illustrates how the offset of a target instruction is extracted from the first far taken branch according to one embodiment.

FIG. 1F shows a use of a guest indirect target cache (GITC) according to one embodiment.

FIG. 1G illustrates system operation when a loop-back branch instruction whose target is located in the same cache line in which it resides is encountered according to one embodiment.

FIG. 1H illustrates the operation of an exemplary loop exit instruction tag table A according to one embodiment.

FIG. 1I shows the duplication of a cache line and the forwarding of the cache line and the duplicate cache line according to one embodiment.

FIG. 1J illustrates operations performed by a system for supporting wide and efficient front-end operation with guest-architecture emulation according to one embodiment according to one embodiment.

FIG. 1K illustrates target verification operations performed by a system for supporting wide and efficient front-end operation with guest-architecture emulation when a guest indirect branch is encountered according to one embodiment according to one embodiment.

FIG. 1L illustrates operations performed by a system for supporting wide and efficient front-end operation with guest-architecture emulation when a loop is encountered according to one embodiment according to one embodiment.

FIG. 2 shows components of a system for supporting wide and efficient front end operation with guest architecture emulation according to one embodiment.

FIG. 3A shows a flowchart of the method that is used when a first far taken branch is requested according to one embodiment.

FIG. 3B shows a flowchart of the method that is used when a guest branch instruction is not a function of the position of the current guest instruction pointer according to one embodiment.

FIG. 4 shows a flowchart of the method that is used when a loop is encountered according to one embodiment.

It should be noted that like reference numbers refer to like elements in the figures.

DETAILED DESCRIPTION

Although the present invention has been described in connection with one embodiment, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims.

In the following detailed description, numerous specific details such as specific method orders, structures, elements, and connections have been set forth. It is to be understood however that these and other specific details need not be utilized to practice embodiments of the present invention. In other circumstances, well-known structures, elements, or connections have been omitted, or have not been described in particular detail in order to avoid unnecessarily obscuring this description.

References within the specification to “one embodiment” or “an embodiment” are intended to indicate that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrase “in one embodiment” in various places within the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.

Some portions of the detailed descriptions, which follow, are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals of a computer readable storage medium and are capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “reading” or “fetching” or “computing” or “determining” or the like, refer to the action and processes of a computer system, or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories and other computer readable media into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

Exemplary Operating Environment of Systems and Apparatus for Supporting Wide and Efficient Front-End Operation with Guest-Architecture Emulation According to One Embodiment

FIG. 1A shows an exemplary operating environment 100 of a system 101 for supporting wide and efficient front-end operation with guest-architecture emulation according to one embodiment. System 101 includes subsystems 101A and 101B. Subsystem 101A uses data that is maintained in an information cache to determine whether a first cache line and a non-consecutive cache line (located at the first far taken branch target address and copied into a shadow cache) or the first cache line and a cache line that follows the first cache line are to be fetched. Subsystem 101B identifies cache lines that contain dynamically taken branches, and duplicates such cache lines, such that these cache lines and their duplicate cache lines can be forwarded together in pairs. Moreover, subsystem 101B determines the point at which a loop that involves one or more cache line pairs is exited by referencing an exit branch instruction identifying table. A matching tag in the table indicates that a branch instruction of a duplicate cache line is to be treated as the exit branch of the loop. Based on the aforementioned operations, systems 101A and 101B facilitate the maintenance of efficient processor frontend supply of multiple cache lines of instructions to the processor scheduler and execution units during each clock cycle, even where first far taken branches and loops are encountered (discussed herein in detail below). FIG. 1A shows system 101, first far taken branch managing system 101A, loop managing system 101B, level one (L1) cache 103, instruction cache 103a, first far taken branch data table (FFTB DT) 103b, shadow cache 103c, cache controller 105, CPU 107, level two (L2) cache 109, system interface 111 and main memory 113.

Referring to FIG. 1A, level one (L1) cache 103 is the primary cache of CPU 107 and is static memory which can be integrated with the processor core. Moreover, L1 cache 103 is used to store information that has been recently accessed by CPU 107. In one embodiment, L1 cache 103 can include instruction cache 103a, first far taken branch data table (FFTB DT) 103b and shadow cache 103c. In one embodiment, instruction cache 103a stores executable instructions of programs that can include first far taken branch (FFTB) instructions. And, shadow cache 103c stores copies of the cache lines that are stored at the target addresses of FFTB instructions of application programs. For example, as shown in FIG. 1B, shadow cache 103c can store a copy of a cache line Y that is stored at the predicted target address of a FFTB instruction of cache line X. Moreover, because cache line Y is stored in the same index in shadow cache 103c as is the FFTB instruction that is stored in instruction cache 103a, these non-consecutive cache lines can be fetched in the same clock cycle and can be forwarded together (such as to the processor scheduler and execution units). In one embodiment, shadow cache 103c can have the same number of sets and half the number of ways as does instruction cache 103a. In other embodiments, other configurations of shadow cache 103c with different numbers of sets and ways can be used.

As regards, FFTB DT 103b, in one embodiment, as shown in FIG. 1C, the FFTB DT 103b stores data that can include but is not limited to FFTB target addresses (the addresses of the cache lines where instruction fetch restarts after the fetch of the cache lines that contain the FFTB), instruction offsets of FFTB target addresses, guest/native instruction identifiers and direct/indirect instruction identifiers. In one embodiment, when a cache line is brought from L2 cache 109 and placed into L1 cache 103 the aforementioned data can be decoded from the cache line and placed into FFTB DT 103b.

In one embodiment, based on a FFTB target address that is calculated and cached in FFTB DT 103b, when a cache line that contains an FFTB is fetched, the cache line at the cached target address is fetched from shadow cache 103c as the second cache line (as opposed to the cache line that follows the cache line that contains the FFTB as part of a consecutive code fetch) as is described in detail herein below.

Referring again to FIG. 1A, cache controller 105 includes the logic used to control cache memory units and to carry out predetermined cache policies. In one embodiment, systems 101a and 101b, described herein in detail below, and their functionality can be provided as a part of cache controller 105. In other embodiments, system 101a and system 101b, or components thereof, can be separate from cache controller 105.

Level 2 cache 109 is secondary cache but like L1 cache 103 is used to store recently accessed information. In one embodiment, as discussed above, a cache-line that is stored in L2 cache 109 can be brought from L2 cache 109 and placed into L1 cache 103. Moreover, as discussed above, when the cache line is brought from L2 cache 109, data can be decoded from the cache line and placed into FFTB DT 103b.

Also shown in FIG. 1A is main memory 113 and system interface 111. Main memory 113 includes physical addresses that store information that can be copied into cache memory and system interface 111 facilitates the transfer of data between main memory 113 and L2 cache 109.

First Far Taken Branch Managing Subsystem

Referring to FIG. 1A, system 101A enables the forwarding of multiple cache lines of instructions to the processor scheduler and execution units (not shown) during each cycle, even where first far taken branches are encountered. In one embodiment, system 101A uses data that is maintained in FFTB DT 103b to determine whether a first cache line (that contains a first far taken branch) and a cache line stored in shadow cache 103c (that is a copy of a cache line that is stored at the target of the first far taken branch) or a first cache line and a cache line that follows the first cache line are fetched. More specifically, referring to FIG. 1D, as a part of its operation, system 101A, upon receiving a request to fetch a first far taken branch instruction, reads a first cache line (cache line X) which contains the first far taken branch instruction, a next cache line (cache line X+1) and a cache line (cache line Y) that is stored in shadow cache 103c that is a copy of the cache line stored at the first far taken branch instruction target address. Thereafter, system 101 fetches the first cache line (cache line X) and either the next cache line (cache line X+1) or the cache line (cache line Y) stored in shadow cache 103c based on information accessed from FFTB DT 103b.

As shown in FIG. 1E, in order to confirm that the target address that is stored in FFTB DT 103b is valid, system 101A accesses the offset of the first far taken branch instruction in the cache line X from FFTB DT 103B, and using this offset, extracts from the first far taken branch the offset of the target. Thereafter, guest target computer 120 computes a guest target address based on the offset of the target instruction and data that is provided by the guest instruction pointer (not shown in FIG. 1E). The computed guest target address G_tc and the native target address N_ts that is stored in FFTB DT 103b are forwarded together to native/guest target mapping table 122 (e.g., conversion-lookaside-buffer-CLB). There, a comparison of these addresses with the current mapping of the guest target address G_tm and the native target address N_tm that is present in native/guest target mapping table 122 is made in order to determine if the computed guest target address G_tc and the stored native target address N_ts are valid (see FIG. 1E). In one embodiment, a confirmation of the validity of this data is made each time a cache line containing a first far taken branch and the cache line stored at its target address are fetched (because the cache line previously stored at the target address may have been replaced with another cache line during the period between fetches).

In one embodiment, when the location of a guest branch instruction is not a function of the current guest instruction pointer (e.g., the guest branch instruction is a guest indirect branch instruction), an additional caching structure, referred to herein as a “guest indirect target cache” (GITC) 103d, can be used to store a predicted guest target address of the guest indirect branch instruction as is shown in FIG. 1F. In one embodiment, GITC can be provided as a part of L1 cache 103. In one embodiment, FFTB-DT 103b can store information that can be used to identify a branch instruction as a guest indirect branch instruction. Moreover, in one embodiment, FFTB-DT 103b can also store information that identifies the way in which the predicted guest target is stored in GITC 103d. In one embodiment, when a branch instruction is identified as a guest indirect branch instruction, this way can be used to select a predicted guest target G_tp from the set associative GITC 103d as is shown in FIG. 1F. In one embodiment, the predicted guest target G_tp can be forwarded to native/guest target mapping table 122 and its validity determined by comparing the predicted guest target G_tp to the current guest target mapping in native/guest target mapping table 122.

Loop Managing Subsystem

In one embodiment, to maximize cache line forwarding where small loops are encountered, pre-decoded bits can be stored that indicate that although two consecutive cache lines, cache line X and cache line X+1, can be forwarded, the next instruction fetch is expected to be to the same cache-line as shown in FIG. 1G. In one embodiment, system 101B determines if a branch instruction BR A of a first cache line X is dynamically taken (e.g., is successively taken) and replicates cache line X if it is determined that the branch instruction BR A of cache line X is indeed dynamically taken as is shown in FIG. 1G. In such cases, cache line X and the duplicated cache line (e.g., cache line Z in FIG. 1G) are selected to be forwarded together. And, a loop exit branch instruction tag table (discussed herein in detail below) is used to predict the direction of the second instance of branch instruction BR A, BR A′, that is located in the duplicated cache line. Thus, in one embodiment, regardless of the direction of BR A, two cache-lines of instructions can be processed and forwarded to the scheduler (either cache line X and cache line X+1 which contains the fall through of BR A or cache line X and duplicate cache line Z which contains BR A′ as is shown in FIG. 1G).

In a wide architecture that is able to forward two cache lines every clock cycle, the two instances of the backward branch, namely, BR A and BR A′ (the instances in the first cache line and the duplicated cache line) can be fetched at the same time. A component that is used in branch prediction, a Global History Shift Register (GHSR), is an m-bit shift register that records the direction (taken or not taken) of the last m branch instructions that are encountered by the processor. It should be appreciated that because a GHSR is updated once at the end of each cycle, a direction prediction (a prediction regarding whether a branch instruction is taken or not taken) for both BR A and BR A′ may be made by a branch predictor using the same GHSR content. Because of this, if BR A′ is the exit branch of the loop, the loop exit may be mis-predicted because of the reliance of the branch prediction logic on a GHSR that corresponds to taken branch, BR A, in making the prediction. This type of mis-prediction is avoided if BR A is the exit branch of the loop.

In one embodiment, in order to avoid mis-predictions of the type discussed above, a table (as alluded to above) is used that includes data that enables the direct identification of exit branch instructions that otherwise can be mis-predicted. FIG. 1H shows an example of such a table, Table A (a loop exit branch instruction tag table). FIG. 1H illustrates the operation of Table A, which maintains entries, that correspond to respective loops A-N, and that include respective tags that are used to identify the exit instruction for the loops. The tags that are stored in Table A are a combination of the PC (e.g., program counter) bits and the GHSR content that correspond to loop exit branch instructions. In one embodiment, a validity confirmation bit for each table entry is stored in Table A to confirm whether a table entry is valid. In one embodiment, any suitable replacement policy (e.g., pseudo-least-recently-used) can be used to maintain Table A. In one embodiment, during a fetch, the processor front end can indicate that a branch instruction is the second instance of a loop-back branch instruction (e.g., branch instruction BR A′ in the foregoing example) that is being fetched that cycle (as was discussed with reference to FIG. 1G). A bit that identifies the second instance of the loop-back branch instruction can then be stored during the lifetime of the branch. If the second instance loop-back branch instruction is thereafter mis-predicted, as taken, and a bit identifying the second instance loop-back branch instruction is set (and there is no entry in Table A for the branch), the PC and GHSR information corresponding to the loop-back branch instruction (which is then known as corresponding to the loop exit branch instruction based on its mis-prediction as being taken) is inserted into Table A (see FIG. 1H; tag for loop N). In one embodiment, “exclusive or” logic can be used to compress the PC and GHSR information.

In one embodiment with PC and GHSR information stored as tags in Table A that correspond to second instance loop-back branch instructions, Table A can be accessed during fetch operations to correct the direction of mis-predicted second instance loop-back branch instructions. A hit in Table A means that the direction of a branch should be corrected from taken to not taken (to exit the loop) even if the branch predictor predicts that the direction is taken (a hit in Table A overrides the branch predictor).

In summary, referring to FIG. 1I, as a part of its operation, system 101B, responsive to a request to fetch a cache line X that includes a branch instruction BR A, determines if BR A is to be successively executed as a part of a loop. If it is determined that BR A is to be successively executed, system 101B creates a duplicate of the cache line X, cache line Z, that includes a branch BR A′ and forwards both cache line X and cache line Z as is shown in FIG. 1I. As a part of determining whether branch BR A′ is a taken or not taken branch, system 101B, determines if BR A′ has a PC value and a GHSR pattern and that matches that of a PC value and a GHSR pattern of an exit branch instruction tag that is stored in Table A as shown in FIG. 1I (such as the tag that corresponds to Loop A). If branch BR A′ has a PC value and GHSR pattern that matches that of a PC Value and GHSR pattern of an exit branch instruction tag that is stored in Table A, the loop is exited (cache line X and cache line X+1 containing the fall-through branch of BR A are forwarded). However, if branch BR A′ does not have a PC value and GHSR pattern that matches that of a PC value and GHSR pattern of an exit branch instruction tag that is stored in Table A, cache line X and its duplicate cache line Z are again forwarded, and the above described cache line duplicating, forwarding and exit branch identifying operations are repeated.

In one embodiment, because the content of table A can be configured to be valid for up to a predetermined maximum number of iterations per loop, a saturation check can be performed before a pattern is inserted into the table. For example, for a loop GHSR having a maximum number iterations of 0xfff, a false positive hit can occur for instances of the loop greater than 12 because all iterations of the loop greater than 12 will see a value of 0xfff in GSHR and match the contents of the table. This can cause a misidentification of a branch as an exit branch. Accordingly, a saturation check of GHSR should be performed before insertion of data into Table A. In one embodiment, in addition to the previously described features, system 101B can include loop unrolling logic to save space in the shadow cache.

Operation

FIGS. 1J-1L illustrates operations performed by system 101 for supporting wide and efficient front-end operation with guest-architecture emulation according to one embodiment. These operations, which relate to wide and efficient front-end operation with guest-architecture emulation are only exemplary. It should be appreciated that other operations not illustrated by FIGS. 1J-1L can be performed in accordance with one embodiment.

First Far Taken Branch Managing Operations (Direct)

Referring to FIG. 1J, at A, system 101A, upon receipt of a request to fetch a first far taken branch, reads a first cache line (cache line X) that includes a first far taken branch, a next cache line (cache line X+1) and a cache line (cache line Y) that is stored at a target address in instruction cache 103A and is copied to an index of shadow cache 103C.

At B, system 101A fetches the first cache line and either the next cache line or the cache line located in shadow cache 103C based on information accessed from the FFTB DT 103b. In the FIG. 1J example, at B, cache line X and non-consecutive cache line Y (the cache line that is stored at the branch target and in shadow cache 103C) are fetched. Thus, in the FIG. 1J example, information is accessed from FFTB DT 103b that indicates that cache line Y as opposed to cache line X+1 is to be fetched.

The requirement of providing high throughput in an emulated architecture leads to complex data paths (such as are presented by far taken branches and loops). To address this, in one embodiment, the frontend can be required to decode both guest and native branch instructions. The guest branches can then be used to calculate the guest targets and to lookup a native/guest target mapping table to obtain native targets that can be cached in FFTB DT 103b. In one embodiment, data from FFTB DT 103b can be used to select a FFTB from which information can be obtained to compute a guest target. In one embodiment, the cached native target and the computed guest target can be validated by comparing them to data in the native/guest target mapping table as is described below in operations C-F.

At C, system 101A, determines the offset of a first far taken branch of the first cache line (cache line X) in instruction cache 103a from FFTB DT 103b. In one embodiment, the offset of the first far taken branch is data that is pre-decoded and stored in the FFTB DT 103B.

At D, system 101A extracts the offset of the target instruction relative to the first far taken branch from the first cache line.

At E, system 101A computes a guest target value based on the offset of the target instruction and a value that is associated with the guest instruction pointer. The computed guest target and the cached native target are provided to native/guest target mapping table such that a comparison with the mapping that is maintained therein can be made (see below).

At F, system 101A compares the computed guest target address and the cached native target address (cache in FFTB DT 103b in FIG. 1A) with the current operating system mapping of the guest target address and the native target address present in the native/guest target address mapping table (e.g., 122 in FIG. 1F) to determine if the computed guest target address and the cache native target address are valid.

First Far Taken Branch Managing Operations (Indirect)

Referring to FIG. 1K, at A, information from FFTB-DT 103b is used to identify a branch instruction as a guest indirect branch instruction and to identify the way in which a predicted guest target address is stored in GITC 103d. In one embodiment, GITC 103d can be a part of L1 cache 103.

At B, the way is used to select the predicted guest target address from the set associative GITC 103d.

At C, the validity of the predicted guest target is determined by comparing the predicted guest target value to a value that is stored in the native/guest target mapping table.

Loop Managing Operations

In one embodiment, as discussed herein, a bit that identifies the second instance of a loop-back branch instruction can be stored during the lifetime of a branch. Thus, if a second instance loop-back branch is mis-predicted and the bit identifying the second instance loop-back branch is set (and there is no entry in Table A that corresponds to the second instance loop-back branch), the PC and GHSR information corresponding to the branch is inserted into Table A. Operations A-E of FIG. 1L illustrate operations that occur subsequent to an entry for a branch being placed into Table A.

Referring to FIG. 1L at A, system 101B, responsive to a request to fetch branch instruction BR A of cache line X, determines if branch instruction BR A is to be successively executed as a part of a loop (e.g., determines if the branch is dynamically taken).

At B, if branch instruction BR A is to be successively executed system 101B creates a duplicate of cache line X, cache line Z, and forwards cache line X and cache line Z as is shown in FIG. 1L.

At C, as a part of determining whether branch instruction BR A′ of duplicate cache line Z is a taken or not taken branch instruction, system 101B, determines if BR A′ has a PC value and GHSR pattern that matches that of a stored instruction tag of Table A (see FIG. 1L) that identifies the exit branch (not taken branch) associated with the loop.

At D, if branch instruction BR A′ has a PC value and GHSR pattern that matches that of the stored instruction tag that identifies the exit branch instruction of the loop, the loop is exited (e.g., and cache line X+1 containing the fall-through of BR A is forwarded).

At E, if branch instruction BR A′ does not have a PC value and GHSR pattern that matches that which identifies the exit branch instruction of the loop, then operations B-E are repeated as needed.

Components of System for Supporting Wide and Efficient Front-End Operation with Guest-Architecture Emulation According to One Embodiment

FIG. 2 shows components of a system 101 for supporting wide and efficient front end operation with guest architecture emulation according to one embodiment. In one embodiment, components of system 101 implement an algorithm for wide and efficient front end operation with guest architecture emulation. In the FIG. 2 embodiment, components of subsystem 101A include read request reader 201, fetcher 203, offset determiner 205, target offset extractor 207, target computer 120, target validator 211, guest indirect branch/GITC way identifier 213 and guest target selector 215.

First Far Taken Branch Managing Components

Reader 201 reads a first cache line that includes a first far taken branch instruction (e.g., the fetch pc), a next cache line (e.g., the cache line after the fetch pc) and a cache line stored in a shadow cache upon receiving a request to fetch a first far taken branch instruction. In one embodiment, in every clock cycle, when the instruction cache is accessed for the fetch_pc, three cache lines are read and two are selected to be forwarded (see discussions made herein with reference to FIGS. 1A-1D).

Fetcher 203 fetches the first cache line (e.g., the fetch_pc) and either the next cache line (e.g., a consecutive cache line) or a cache line in the shadow cache (e.g., a non-consecutive cache line) that is located at an index of the shadow cache that corresponds to the index of the instruction cache in which the first cache line is located. In one embodiment, when the cache line that corresponds to the current fetch_pc is fetched, information that is accessed from the FFTB DT (e.g., pre-decoded bits) is used to determine whether the two consecutive cache lines or the two non-consecutive cache lines are processed. In one embodiment, the shadow cache is accessed by the set of the fetch_pc but tagged by the target of the first far taken branch (see discussions made herein with reference to FIGS. 1A-1D).

Offset determiner 205 determines an offset of the first far taken branch in the first cache line. In one embodiment, offset determiner 205 determines the offset of the first far taken branch by accessing this information from the FFTB DT (e.g., 103b in FIG. 1A).

Target offset extractor 207 extracts a target offset from the first far taken branch of the first cache line. In one embodiment, a multiplexor can be used in the implementation of target offset extractor 207. In one embodiment the multiplexer selects the target offset and outputs the target offset to target computer 120. In other embodiments other components can be used in the implementation of target extractor 207.

Target computer 120 computes a guest target based on the target offset and a guest instruction pointer. In one embodiment, target computer 209 can be implemented as is described in commonly assigned U.S. patent application Ser. No. 13/360,024, filed on Jan. 27, 2012, to Mohammad Abdallah et al., entitled “Hardware Acceleration Components for Translating Guest Instructions to Native Instructions”, which is incorporated by reference herein in its entirety.

Target validator 211 determines whether the computed guest target is valid based on an existing mapping of the guest target to a native target that is stored in a native/guest target mapping table (122 in FIG. 1F). In one embodiment, the determination is made by comparing a cached native target address (e.g., from FFTB DT 103b in FIG. 1A) and the computed guest target address with the information that is stored in the native/guest target mapping table (122 in FIG. 1F).

First Far Taken Branch Managing Components (Indirect)

Guest indirect branch/GITC way identifier 213 determines if a branch instruction is a guest indirect branch instruction and identifies the way in a guest-indirect-target cache (e.g., GITC 103d in FIG. 1F) in which a predicted guest target is stored. In one embodiment, the guest indirect branch/GITC way identifier 213 can determine whether a branch instruction is indirect or not by accessing an indicator of such in a first far taken branch data table (e.g., FFTB DT 103b in FIG. 1A).

Guest target selector 215 selects a predicted guest target from a set associative guest-indirect-target cache (e.g., GITC 103d in FIG. 1F). In one embodiment, a multiplexor can be used in the implementation of guest target selector 215. In one embodiment the multiplexer can select the guest target address from the guest-indirect-target cache (e.g., GITC 103d in FIG. 1F), based on the way that is identified by indirect guest branch/GITC way identifier 213, and outputs the predicted guest target for forwarding to a native/guest target mapping table. Using the native/guest target mapping table, the validity of the predicted guest target can be determined.

Loop Managing Components

In the FIG. 2 embodiment, components of subsystem 101B include loop exit branch instruction tag entry inserter 217, loop determiner 219, line duplicator 221, and exit instruction determiner 223.

Referring to FIG. 2, loop exit branch instruction tag entry inserter 217 inserts tags into placeholders of a loop exit branch instruction table (e.g., Table A in FIG. 1H) that identify the exit instructions that correspond to respective loops. As discussed herein, if a second instance loop-back branch is mis-predicted and a bit identifying the branch as a second instance loop-back branch is set (and there is no entry in Table A that corresponds to the second instance loop back branch), loop exit branch instruction tag entry inserter 217 inserts the PC and GHSR information that corresponds to the branch into the loop exit branch instruction tag table (e.g., Table A in FIG. 1H).

Loop determiner 219 determines if a branch instruction is to be successively executed as a part of a loop. In one embodiment, the determination can be made in response to a request to fetch a branch instruction of a first cache line.

Line duplicator 221 creates a duplicate of the first cache line and forwards the first cache line and the duplicate of the first cache line if the branch instruction is determined to be successively executed.

Exit instruction determiner 223 determines if a branch instruction that is included in the cache line that is a duplicate of the first cache line (e.g., the second instance loop-back instruction) has characteristics that correspond to a stored instruction tag that identifies an exit branch (not taken branch) associated with the loop. In particular, if the second instance loop-back instruction has a PC value and GHSR pattern that matches that of a PC value and GHSR pattern that are a part of a stored instruction tag that identifies the exit branch instruction of the loop, the loop is exited. However, if the second instance loop-back branch instruction does not have a PC value and GHSR pattern that matches that of a PC value and GHSR pattern that are part of a stored instruction tag, the first cache line and its duplicate are again forwarded.

It should be appreciated that the aforementioned components of system 101 can be implemented in hardware, software, firmware or in some combination thereof. In one embodiment, components and operations of system 101 can be encompassed by components and operations of one or more computer components or programs (e.g., a cache controller 105). In another embodiment, components and operations of system 101 can be separate from the aforementioned one or more computer components or programs but can operate cooperatively with components and operations thereof. In one embodiment, subsystems 101A and 101B of system 100 can be provided together as a part of an integrated system. In other embodiments, each of subsystems 101A and 101B can be made, used and function separately and independently of the other. Additionally, although specific components are disclosed in the FIG. 2 diagram, such components are exemplary. That is the present embodiment can have various other components or variations of the components shown in the diagram.

Method for Supporting Wide and Efficient Front-End Operation with Guest-Architecture Emulation According to One Embodiment According to One Embodiment

FIGS. 3A, 3B and 4 show flowcharts 300A, 300B and 400 of steps performed in exemplary methods that are a part of a method for wide and efficient front end operation with guest architecture emulation according to one embodiment. The flowcharts include processes that, in one embodiment can be carried out by processors and electrical components under the control of computer-readable and computer-executable instructions. Although specific steps are disclosed in the flowcharts, such steps are exemplary. That is the present embodiment is well suited to performing various other steps or variations of the steps recited in the flowcharts.

FIG. 3A shows a flowchart of the method that is used when the fetching of a first far taken branch instruction is requested.

Referring to FIG. 3A, at 301A, in response to a request to fetch a first far taken branch instruction of a first cache line, the first cache line, the next cache line and a cache line located at the branch target (that has a copy stored in a shadow cache) is read.

At 303A, the first cache line and either the next cache line or the copy of the cache line stored in the shadow cache is fetched based on information accessed from the FFTB DT (e.g., 103B in FIG. 1A).

At 305A, in order to confirm that the cached branch target is valid, the offset of the first far taken branch in the first cache line is determined based on information accessed from the FFTB DT (e.g., 103B in FIG. 1A).

At 307A, a target offset is extracted from the first far taken branch of the first cache line (see FIG. 1E).

At 309A, a guest target address is computed based on the target offset and a guest instruction pointer (see FIG. 1E) and is forwarded along with the cached native target address to the native/guest target mapping table.

At 311A, it is determined whether a computed guest target address and the cached native target address are valid by comparing them with the native/guest target addresses that are stored in the native/guest target mapping table (see FIG. 1E).

FIG. 3B shows a flowchart of the method used when a guest branch instruction is not a function of the current guest instruction pointer (e.g., the guest branch is a guest indirect branch) and an additional caching structure, a guest indirect target cache (GITC), is used to store a predicted guest target of the guest indirect branch instruction.

Referring to FIG. 3B, at 301B, information from a data table (e.g., FFTB-DT 103b in FIG. 1A) is used to identify a branch instruction as a guest indirect branch instruction and to identify the way in which a predicted guest target is stored in the GITC (e.g., 103d in FIG. 1F).

At 303B, the way is used to select the predicted guest target that is stored in the set associative GITC (e.g., 103d in FIG. 1F).

At 305B, the validity of the predicted guest target is determined based on the mapping of the guest target to the native target in the native/guest target mapping table.

FIG. 4 shows a flowchart of the method that is used when a loop is encountered. In one embodiment, as discussed herein, prior to the method sequence described below, PC and GHSR information corresponding to the exit branch instruction of the loop encountered is inserted into Table A. Operations A-E of FIG. 1L illustrate operations that occur subsequent to an entry for a branch being placed into Table A.

Referring to FIG. 4, at 401 responsive to a request to fetch a branch instruction of a first cache line, it is determined if the branch instruction is to be successively executed as a part of a loop. If it is determined that the branch instruction is not to be successively executed, the first cache line and a cache line that includes a fall through branch are forwarded at 409.

At 403, a duplicate of the first cache line is made and the first cache line and the duplicate of the first cache line are forwarded (if the branch instruction is determined to be successively executed).

At 405, it is determined if a duplicate branch instruction that is contained by the duplicate cache line has a PC value and a GHSR pattern that corresponds to a PC value and GHSR pattern that are a part of a stored instruction tag that identifies an exit branch instruction (a not taken branch) associated with the loop.

At 407, if the duplicate branch instruction has a PC value and GHSR pattern that corresponds to a PC value and GHSR pattern that are a part of a stored instruction tag that identifies an exit branch instruction (not taken branch) associated with the loop, the loop is exited.

However, if the duplicate branch instruction does not have a PC value and GHSR pattern that corresponds to a PC value and GHSR pattern that are a part of a stored instruction tag that identifies an exit branch instruction (not taken branch) associated with the loop, 403 is repeated.

With regard to exemplary embodiments thereof, methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

Although many of the components and processes are described above in the singular for convenience, it will be appreciated by one of skill in the art that multiple components and repeated processes can also be used to practice the techniques of the present invention. Further, while the invention has been particularly shown and described with reference to specific embodiments thereof, it will be understood by those skilled in the art that changes in the form and details of the disclosed embodiments may be made without departing from the spirit or scope of the invention. For example, embodiments of the present invention may be employed with a variety of components and should not be restricted to the ones mentioned above. It is therefore intended that the invention be interpreted to include all variations and equivalents that fall within the true spirit and scope of the present invention.

Claims

1. A processor, comprising: a cache system, comprising: a cache controller to: fetch, a first cache line that includes a branch instruction and, based on information in a data table, either a second cache line that is adjacent to the first cache line in the instruction cache or a target cache line that is stored at a target address of the branch instruction,wherein the information is populated in the data table upon moving the first cache line from an L2 cache to an L1 cache,wherein the cache controller is to copy the target cache line to a shadow cache and the target cache line is fetched from the shadow cache, andwherein the shadow cache has a same number of sets and half a number of ways as the instruction cache.

2. The processor of claim 1, wherein the information in the data table is separate from the first cache line, including an indication of the target address in the cache line.

3. The processor of claim 1, wherein the target cache line is stored in a same index of the shadow cache as is the first cache line in the instruction cache.

4. The processor of claim 1, wherein the controller is to determine an offset of a target instruction in the target cache line relative to the branch instruction, compute a guest target based on said offset of said target instruction and a guest instruction pointer, and determine whether said guest target and a cached native target are valid based on a reference to a conversion-lookaside-buffer.

5. The processor of claim 1, wherein the controller to select a predicted guest target from a guest target cache that stores guest targets and determine whether the predicted guest target is valid based on a reference to a conversion-lookaside-buffer.

6. The processor of claim 1, wherein the information includes one or more of a branch instruction address of the branch instruction, an offset associated with the target cache line, a direct/indirect branch instruction identifier, and a native/guest branch instruction identifier.

7. A cache system, comprising: a cache controller to: fetch, a first cache line that includes a branch instruction and, based on information in a data table, either a second cache line that is adjacent to the first cache line in the instruction cache or a target cache line that is stored at a target address of the branch instruction,wherein the information is populated in the data table upon moving the first cache line from an L2 cache to an L1 cache,wherein the cache controller is to copy the target cache line to a shadow cache and the target cache line is fetched from the shadow cache, andwherein the shadow cache has a same number of sets and half a number of ways as the instruction cache.

8. The cache system of claim 7, wherein the information in the data table is separate from the first cache line, including an indication of the target address in the cache line.

9. The cache system of claim 7, wherein the target cache line is stored in a same index of the shadow cache as is the first cache line in the instruction cache.

10. The cache system of claim 7, wherein the controller is to determine an offset of a target instruction in the target cache line relative to the branch instruction, compute a guest target based on said offset of said target instruction and a guest instruction pointer, and determine whether said guest target and a cached native target are valid based on a reference to a conversion-lookaside-buffer.

11. The cache system of claim 7, wherein the controller to select a predicted guest target from a guest target cache that stores guest targets and determine whether the predicted guest target is valid based on a reference to a conversion-lookaside-buffer.

12. The cache system of claim 7, wherein the information includes one or more of a branch instruction address of the branch instruction, an offset associated with the target cache line, a direct/indirect branch instruction identifier, and a native/guest branch instruction identifier.

13. A non-transitory machine-readable storage medium that stores instructions, which when executed by a processor, causes the processor to: fetch, a first cache line that includes a branch instruction and, based on information in a data table, either a second cache line that is adjacent to the first cache line in an instruction cache or a target cache line that is stored at a target address of the branch instruction, wherein the information is populated in the data table upon moving the first cache line from an L2 cache to an L1 cache, andcopy the target cache line to a shadow cache and the target cache line is fetched from the shadow cache,wherein the shadow cache has a same number of sets and half a number of ways as the instruction cache.

14. The non-transitory machine-readable storage medium of claim 13, wherein the information in the data table is separate from the first cache line, including an indication of the target address in the cache line.

15. The non-transitory machine-readable storage medium of claim 13, wherein the target cache line is stored in a same index of the shadow cache as is the first cache line in the instruction cache.

16. The non-transitory machine-readable storage medium of claim 13, wherein the controller is to determine an offset of a target instruction in the target cache line relative to the branch instruction, compute a guest target based on said offset of said target instruction and a guest instruction pointer, and determine whether said guest target and a cached native target are valid based on a reference to a conversion-lookaside-buffer.

17. The non-transitory machine-readable storage medium of claim 13, wherein the information includes one or more of a branch instruction address of the branch instruction, an offset associated with the target cache line, a direct/indirect branch instruction identifier, and a native/guest branch instruction identifier.