Claims
- 1. A multilevel interconnect structure for an integrated circuit device formed in a semiconductor substrate structure, the structure comprising:a first dielectric layer formed over the integrated circuit device, the first dielectric layer having a dielectric constant less than three; a first patterned methylated oxide hardmask formed on the first dielectric layer, the first methylated oxide hardmask defining an opening in the first dielectric layer; and conductive material formed in the opening.
- 2. The structure of claim 1, and wherein the first methylated oxide hardmask has a dielectric constant less than three.
- 3. The structure of claim, and further comprising:a diffusion barrier layer over the integrated circuit device, the first dielectric layer being formed on the diffusion barrier layer.
- 4. The structure of claim 1, and further comprising:a second dielectric layer formed on the first methylated oxide hardmask, the second dielectric layer having a dielectric constant less than three; a second methylated oxide hardmask formed on the second dielectric layer, the second methylated oxide hardmask defining an opening in the second dielectric layer; and conductive material formed in the opening.
- 5. The structure of claim 4, and wherein the second methylated oxide hardmask has a dielectric constant less than three.
- 6. The structure of claim 4, and further comprising:a diffusion barrier layer formed over the integrated circuit device, the first dielectric layer being formed on the diffusion barrier layer.
Parent Case Info
This applications is a divisional of U.S. application Ser. No. 09/294,914, filed Apr. 19, 1999, now U.S. Pat. No. 6,218,317.
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