Claims
- 1. A method for interconnecting a second level packaging of an electronic array module to a printed circuit board or card which comprises attaching said module to said board or card by providing a plurality of solder interconnections extending from solder wettable pads on a major surface of said module to a corresponding set of solder wettable pads of said board or card in a micro area grid array having a pitch of about 0.75 mm or less and wherein said solder interconnections are column shaped with the height of each being at least about 1.4 times its diameter;wherein said connections are about 9 mils to about 13 mils in diameter and about 12.5 mils to about 33 mils in height.
- 2. The method of claim 1 wherein the pitch of the array of said connections is about 0.5 mm to about 0.75 mm.
- 3. The method of claim 1 wherein said solder connections are non-collapsible at the temperature employed to fabricate the interconnection.
- 4. The method of claim 3 wherein said temperature is at least about 220° C.
- 5. The method of claim 1 wherein the height of said connections is up to about 2.5 times the diameter of said connections.
- 6. The method of claim 1 wherein the height of said connections is about 1.5 to about 2.5 times the diameter of said connections.
- 7. The method of claim 1 wherein each column is about the same height and substantially the same diameter throughout each column.
- 8. The method of claim 1 wherein said columns are an alloy of about 90% by weight lead and about 10% by weight tin.
- 9. The method of claim 1 wherein said module comprises a ceramic substrate.
- 10. The method of claim 1 wherein said module comprises an organic polymer substrate.
- 11. The method of claim 1 wherein said connections are about 12.5 mils in diameter and at least about 17.5 mils in height.
CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional of U.S. patent application Ser. No. 09/035,538 filed Mar. 5, 1998 now U.S. Pat. No. 6,059,173.
US Referenced Citations (16)