The present disclosure is related generally to microfabrication and more particularly to a method of microassembly involving transfer printing and thermal joining.
Photolithography has been the dominant manufacturing technique in micro/nano scale manufacturing due to its parallel and batch process nature. The convenience in scalability has significantly reduced the unit cost of individual microelectromechanical systems (MEMS) and integrated chips (IC), enabling broader adaptation of devices ubiquitously found in our everyday lives. While enhanced exposure techniques and the development of various photoresists (PR) have enabled the miniaturization of IC devices down to the nanometer regime, the form factor of such devices is generally limited to two dimensions owing to the planar characteristics of the photolithography process.
Microscale devices with a three-dimensional (3D) form factor have found application in microsystems such as radiofrequency (RF) MEMS switches, mechanical resonators, gyroscopes and pressure sensors, to name a few, due to the inherent advantages of 3D architectures. However, as indicated, fabricating devices with 3D form factors present a challenge for photolithographic patterning methods. For improved performance (e.g., higher sensitivity), such 3D devices may benefit from delicately suspended structures, which are typically achieved by removal of a sacrificial layer buried beneath the structures. Another challenge is integrating heterogeneous materials in MEMS and IC devices using microfabrication given the disparate process parameters of different classes of materials.
Microassembly methods, such as transfer printing, may overcome drawbacks of monolithic microfabrication and permit novel 3D architectures to be fabricated for microsystems. In the early stages of the development of transfer printing, flat surfaced polydimethylsiloxane (PDMS) stamps were utilized to transfer objects onto target receiving sites. Such flat-surfaced PDMS stamps control adhesion by exploiting the viscoelastic nature of the stamp material, yet with bounded reversibility. For this reason, to promote successful transfer printing, highly adhesive receiver substrates were adopted. However, such highly adhesive surfaces are generally polymeric, which limits applications for functional microsystems. The development of various stamps that exhibit a high adhesion on/off ratio has been important to expand the applicability of transfer printing for microsystem fabrication; however, further advancements are needed.
A method for microassembly of heterogeneous materials comprises contacting a stamp with a solid-phase ink disposed on a donor substrate to form an inked stamp, where the solid-phase ink is reversibly bound to the stamp. The inked stamp is stamped onto a receiving substrate or onto an object on the receiving substrate, and the stamp is removed, thereby transferring the solid-phase ink to the receiving substrate. The solid-phase ink is then thermally joined with the object or the receiving substrate to form a microassembly of heterogeneous materials. The object on the substrate may be a previously deposited solid-phase ink. Throughout the disclosure and claims, the terms “solid-phase ink” and “ink” may be used interchangeably.
A method of fabricating a polymeric ink on a donor substrate for transfer printing includes: coating a sacrificial layer onto a silicon substrate; coating a polymeric material on the sacrificial layer and curing to form a polymer layer; patterning the polymer layer to form a polymeric ink pattern; and removing the sacrificial layer, thereby forming the polymeric ink.
A method of fabricating a SiO2 ink on a donor substrate for transfer printing includes: growing a SiO2 layer on a silicon layer; patterning the SiO2 layer to form a SiO2 ink pattern on the silicon layer; patterning the silicon layer to form a silicon pattern laterally surrounding and underlying the SiO2 ink pattern, thereby exposing a buried oxide layer away from the SiO2 ink pattern; covering the SiO2 ink pattern with photoresist and forming one or more photoresist anchors to the buried oxide layer; and removing the silicon pattern, thereby forming the SiO2 ink.
Micro-assembly, which involves sequential transferring and joining of individual micro-scale materials, may overcome shortcomings of monolithic microfabrication and enable novel 3D architectures for microsystems. Transfer printing, inspired from micro contact printing, may utilize the highly reversible surface adhesion of a polymeric manipulator (called a “stamp”) to deterministically transfer microscale solid objects (called “solid-phase inks” or “inks”) in a dry manner. The ability to transfer inks from a donor substrate where inks are grown and processed to a receiving substrate where inks are thermally bonded reduces the complexity of manufacturing processes required for heterogeneous material integration. Furthermore, the dry nature of transfer printing enhances the process compatibility with other manufacturing techniques.
Microassembly of four different classes of materials semiconductors (e.g., Si), metals (e.g., Au), dielectrics (e.g., SiO2) and polymers (e.g., SU-8) is described in this disclosure. For broader utilization of the microassembly process, SiO2 and SU-8 materials are newly developed as inks. The microassembly method employs reversible adhesion-based transfer printing and thermal processing-based material joining. The interfacial joining characteristics between dissimilar materials are quantitatively studied through blister tests to validate the structural integrity of assembled structures and devices (microassemblies). This work demonstrates the use of microassembly to fabricate 3D heterogeneous microsystems, with relevance not only to MEMS but also to electronics, photonics, metamaterials, and other fields. Furthermore, the microassembly process can complement conventional micromachining techniques by transfer printing and joining an individual constituent of a device at spatially organized sites for enhanced performance or novel functionalities.
Referring now to
The inked stamp 108 (i.e., the stamp 106 and the ink 102 reversibly bound to the stamp 106) is removed from the donor substrate 104, as illustrated in
As indicated above, the stamp 106 is capable of reversibly binding the ink 102. More specifically, the stamp 106 may comprise a material that exhibits minimal adhesion to the ink 102; the adhesion is sufficient to allow for transportation of the ink 102 on the stamp 106 but also release of the ink 102 upon removal of the stamp 106 from the receiving substrate 110. For example, the stamp 106 may comprise a material with viscoelastic properties, such as polydimethylsiloxane (PDMS) or another polymer.
The method may further include repeating the contacting and stamping to add additional inks 102 to the receiving substrate 110. The microassembly 100 may include at least two of the inks 102 stacked on the receiving substrate 110, as shown schematically in
The repeating of the contacting and stamping to incorporate multiple inks 102 in the microassembly 100,200 (e.g., as shown in
Thus, the ink(s) 102 and the receiving substrate 110 may be thermally joined by heating at a suitable temperature determined in full or in part by the materials being joined. In one example, the first (ink) material comprises SiO2 and the second (receiving substrate) material may be SU-8 or Si. In another example, the first material comprises SU-8 and the second material may be SiO2, Si, and Au. Examples of thermal joining conditions for different ink-receiving substrate pairs are set forth in Table 1. The bonding mechanism depends on the materials and may be described as fusion, eutectic or adhesive bonding, as summarized in Table 2.
Generally speaking, thermal joining is carried out at a temperature in a range of about 125° C. to about 1000° C., about 150° C. to about 1000° C., about 300° C. to about 1000° C., or about 600° C. to about 1000° C. The thermal joining may take place at a temperature of at least about 125° C., at least about 150° C., at least about 300° C., at least about 500° C., at least about 600° C., or at least about 900° C., depending on the materials involved. The thermal joining temperature may also be no greater than 200° C., no greater than 400° C., no greater than 700° C., or no greater than 1100° C., depending on the materials involved. For example, a SiO2 ink may be joined to a Si receiving substrate by heating at a temperature in a range from about 900° C. to 1100° C. If, however, the Si receiving substrate first undergoes activation with oxygen, thermal joining with the SiO2 ink may be carried out at a lower temperature in a range from about 500° C. to about 700° C. In another example, the SiO2 ink may be joined to a SU-8 receiving substrate by heating at a temperature in range from about 125° C. to about 175° C. In yet another example, a SU-8 ink may be joined to a receiving substrate comprising Si, SiO2 or Au by heating at a temperature in a range from about 125° C. to about 175° C. As would be recognized by the skilled artisan, the temperature ranges given above apply to the material pairs regardless of which is the ink and which is the receiving substrate.
Generally speaking, the heating may be carried out for 30 minutes or less, 20 minutes or less, 10 minutes or less, or five minutes or less, and typically for at least about 0.5 minute or at least about 1 minute to effect bonding. Typically, the heating/thermal joining is carried out for 5 to 15 minutes. The thermal joining may take place in air or a controlled environment, e.g., inert gas or vacuum.
An advantage of the method is that application of pressure is not required during thermal joining. In contrast, in wafer scale joining, two objects are brought into contact and exposed to a preload during heating to promote intimate contact. The process does not require external forces during thermal processing since typical inks are significantly smaller than wafers, such that intermolecular forces between inks are strong enough to maintain sufficient surface contact. These dominant intermolecular forces may originate from reduced defects present in the small contact area when compared to wafer-scale bonding areas.
To demonstrate the integrity of bonded interfaces, microassemblies formed by transfer printing and thermal joining are evaluated with blister testing as described below, Experimental assessment of the interfacial joining strength between printed inks/substrates can not only ensure the robustness of assemblies constructed through microassembly but also allow a comparison between various mechanisms to join different materials at the microscale. Blister tests have been successfully utilized to characterize the adhesion of thin films formed on Si substrates and are utilized in this disclosure for measuring the joining strength at Si—Si, Si—SiO2, Si—Au and Si-SU-8 interfaces of the microassemblies.
Gc=G(pc)=0.625pcdc (1)
where Gc is a function of material properties of the ink and the receiving substrate and is termed critical energy release rate or toughness, which indicates the material's resistance to fracture along any given path. Provided that the ink delaminates along the joining interface, the corresponding Gc indicates the toughness of the joining. The energy release rate G, on the other hand, is a loading parameter indicating the driving force for fracture. For the specimen geometry here, G is simply a function of the applied pressure pc and the central deflection of the ink dc. Finite element analysis (FEA) is conducted to determine dc that is a function of measured pc, specimen dimensions and material properties. At the moment when the Si ink delamination occurs, G reaches the toughness Gc. Upon failure, the critical pressure Pc is measured and the corresponding deflection dc is obtained through simulation, as shown in
A full description of blister test specimen fabrication, joining conditions and testing procedures is provided below in reference to
Three specimens are tested per each joining material pair and the resultant Gc are plotted in
While thermal processing conditions for material joining in microassembly may be inspired by conventional wafer bonding techniques, optimal wafer-scale thermal processing conditions do not necessarily apply to microassembly processes. For example, an assembled Si—SiO2 structure may fail to retain its original structure after thermal processing because of different thermal expansion coefficients between Si and SiO2. In this case, a relatively low thermal processing temperature (600° C.) in conjunction with oxygen plasma surface activation may be exercised in microassembly. To reproduce such a process for a blister test specimen, a SiO2 coated receiving substrate may be activated using oxygen plasma followed by transfer printing and thermal processing. The test results yield 0.3 J/m2, which is lower than for Si—SiO2 pair joined at the temperature of 1000° C., but still on par with other known wafer-scale joining strength values. Similarly, the joining strength between Si and acetone-treated SU-8 is separately studied since SU-8 inks for microassembly are prepared by releasing SU-8 inks in acetone bath. As expected, the acetone treatment on SU-8 can reduce the joining strength in comparison with an unadulterated Si to SU-8 interface, but it is still on the same order of magnitude with all other obtained joining strength data. In summary, the joining strength data obtained through blister tests (as shown in
The applications of microassembly are enhanced by the development of methods to fabricate SU-8 and SiO2 as inks, as shown in
SU-8 is processed to ink format as illustrated in
Microassembly Procedure
Si, Au, SiO2 and SU-8 inks may be prepared on individual donor substrates as shown in
An exemplary donor substrate 104 including four inks 102 is shown in
Microassembly of Blister Test Specimens
Receiving substrates with rims covered or formed by four different materials are made as depicted in
Assembly Procedure of a Vertical Si Ring on a SU-8 Block
Si ring-shaped inks are prepared on a donor substrate and retrieved by a PDMS microtip stamp. On one side of the retrieved ring shaped ink, normal force is applied in a horizontal direction, which causes delamination of ink from the stamp and the ink is attached vertically on an adjacent side of the stamp. Afterwards, the vertically adhering ink is transferred and joined on an SU-8 block to form a 3D Si/SU-8 structure, as shown in
Si Ink Fabrication
1. Determine an SOI wafer based on top Si layer thickness requirement and buried oxide (BOX) layer of 1 μm (Ultrasil), as shown in
2. Pattern AZ 5214 photoresist (PR: AZ electronic materials) by first spinning at 3000 rpm for 30 seconds, followed with soft baking at 110° C. for 1 minute. Once the PR is soft baked, expose using I-line UV (Karl Suss MJB 3) for the dose of 130 mJ/cm2 and develop using 917 MIF developer (AZ electronic materials) for approximately 20 seconds.
3. Pattern Si device layer using reactive ion etching (RIE: PlasmaTherm: 40 sccm SF6, 50 mTorr, 100 W, 3 minutes), as shown in
4. Remove photoresist masking layer and pattern second mask pattern using AZ 5214 PR for selective undercut protection. Identical procedure as step 2 is used for patterning the PR.
5. Post exposure bake at 110° C. for 60 seconds, as shown in
6. Place the substrate in 49% Hydrofluoric Acid (HF: Sigma-Aldrich) for 55 seconds, as shown in
7. Remove photoresist and construct AZ 5214 PR anchor through identical procedure as in step 2, as shown in
8. Post exposure bake of the PR anchors at 110° C. for 90 seconds.
9. Leave the substrate for sufficient time in 49% HF bath for complete removal of BOX layer underneath the Si pattern, as indicated in
Au Ink Fabrication
1. An Si wafer (University wafer) is placed inside furnace to grow ˜1 μm of thermal oxide layer (Lindberg Hevi-Duty Lancer M-300) at 1100° C. with 6 sccm O2 for 48 hours.
2. 5 nm of Ti and 400 nm of Au are sputter (AJA ATC ORION 8HV) deposited (20 sccm Ar, 5×10−3 Torr, 300 W, 1 min for Ti and 20 min for Au), as indicated in
3. Pattern AZ 5214 photoresist (PR: AZ electronic materials) by first spinning at 3000 rpm for 30 seconds, followed with soft baking at 110° C. for 1 minute. Once the PR is soft baked, expose using I-line UV (Karl Suss MJB 3) for the dose of 130 mJ/cm2 and develop using 917 MIF developer (AZ electronic materials) for approximately 20 seconds.
4. Post exposure bake at 110° C. for 1 minute.
5. Place the PR patterned substrate in Au etchant (Sigma-Aldrich) for approximately 2 minutes to pattern Au followed with PR removal, as indicated in
6. Pattern second mask pattern using AZ 5214 PR for selective undercut protection. Identical procedure as step 2 is used.
7. Post exposure bake at 110° C. for 60 seconds, as shown in
8. Place the substrate in 49% Hydrofluoric Acid (HF: Sigma-Aldrich) for 55 seconds, as indicated in
9. Remove photoresist and construct AZ 5214 PR anchor through identical procedure as in 2, as indicated in
10. Post exposure bake of the PR anchors at 110° C. for 90 seconds.
11. Leave the substrate for sufficient time in 49% HF bath for complete removal of buried oxide and Ti sacrificial layer underneath the Au pattern, as indicated in
SU-8 Ink Fabrication
1. Spin coat 495 poly(methylmethacrylate) A resist with 6% in Anisole (PMMA: Microchem) at 3000 rpm and soft bake at 180° C. for 1 minutes, as shown in
2. Spin coat SU8-50 (Microchem) at 3000 rpm and soft bake on hot plate for 65° C. for 6 minutes and 95° C. for 20 minutes, as indicated in
3. Using H-line flood exposure (ABM Flood Exposure Model 60), expose SU8-50 through a pattern mask for 200 mJ/cm2.
4. Post exposure bake at 65° C. for 1 minutes and 95° C. for 5 minutes.
5. Develop using SU-8 developer for 6-10 minutes (MicroChem), as shown in
Submerge the substrate in acetone bath for 1 min for complete removal of PMMA sacrificial layer, as indicated in
SiO2 Ink Fabrication
1. An SOI wafer (Ultrasil) with device layer with 1.5 μm (
2. Pattern AZ 5214 photoresist (PR: AZ electronic materials) by first spinning at 3000 rpm for 30 seconds, followed with soft baking at 110° C. for 1 minute. Once the PR is soft baked, expose using I-line UV (Suss MJB 3) for the dose of 130 mJ/cm2 and develop using 917 MIF developer (AZ electronic materials) for approximately 20 seconds.
3. Post exposure bake at 110° C. for 1 minute.
4. Place the substrate in 49% HF (Sigma-Aldrich) for 55 seconds, as indicated in
5. Remove PR masking layer and Pattern AZ 5214 PR for device layer patterning following the identical procedure as in step 2. This second PR pattern is designed to be approximately 10% larger in lateral dimension than previous oxide pattern in order to protect SiO2 layer during RIE process.
6. Pattern Si device layer using reactive ion etching (RIE: PlasmaTherm: 40 sccm SF6, 50 mTorr, 100 W, 3 minutes) and remove PR, as indicated in
7. Construct AZ 5214 PR anchor using the identical procedure as in step 2. The pattern needs to completely cover patterned thermally grown SiO2 layer as well as some anchors that extends out to buried oxide layer, as shown in
8. Place the substrate in XeF2 etcher (Xactix) for 30 cycles that runs 3 Torr XeF2, 50 seconds per cycle for complete removal of Si device layer that served as sacrificial layer, as indicated in
Elastomeric Microtip Stamp Fabrication
1. On {100} Si substrate (University Wafer), deposit 50 nm of Si3N4 using PECVD (STS systems USA Inc) with medium frequency (1960 sccm N2, 40 sccm SiH4, 35 sccm NH3, 650 mTorr, 300° C. platen and 240° C. showerhead temperatures, 13.56 MHz 20 W 6 seconds and 380 KHz, 20 W 2 seconds per cycle, total of 37 cycles).
2. Pattern AZ 5214 photoresist (PR: AZ electronic materials) by first spinning at 3000 rpm for 30 seconds, followed with soft baking at 110° C. for 1 minute. Once the PR is soft baked, expose using I-line UV (Suss MJB 3) for the dose of 130 mJ/cm2 and develop using 917 MIF developer (AZ electronic materials) for approximately 20 seconds.
3. Post exposure bake at 110° C. for 1 min.
4. Etch Si3N4 using 10:1 buffered oxide etchant (BOE: Sigma-Aldrich) by submerging the substrate in the BOE bath for 150 seconds and remove AZ 5214 PR, as indicated in
5. Place the substrate in potassium hydroxide (KOH: Fisher Scientific), isopropyl alcohol (IPA: Fisher Scientific) and deionized water (DI) mixture bath (70 g KOH, 70 ml IPA and 170 ml DI).
6. Place the KOH bath on 80° C. hot plate for ˜4 hours.
7. Remove the Si3N4 masking layer by submerging in HF (Sigma-Aldrich) bath for 150 seconds, as indicated in
8. Spin coat SU8-50 (Microchem) at 3000 rpm and soft bake on hot plate for 65° C. for 6 minutes and 95° C. for 20 minutes.
9. Using H-line flood exposure (ABM Flood Exposure Model 60), expose SU8-50 through a pattern mask for 200 mJ/cm2.
10. Post exposure bake at 65° C. for 1 minutes and 95° C. for 5 minutes.
11. Develop using SU-8 developer for 6-10 minutes (MicroChem).
12. Place the substrate vertically inside desiccator and apply 3-5 droplets of (Tridencafluoro-1,1,2,2-Tetrahydrooctyl)-1-Trichlorosilane (Trichlorosilane: United Chemical Technology) inside the desiccator.
13. Leave the substrate for 1 hour in vacuum. A monolayer of trichlorosilane is deposited on the surface of the Si/SU-8 substrate as shown in
14. Mix polydimethylsiloxane (PDMS: Sylguard 184, Dow Corning) pre-polymer base and cross-linking agent at 5:1 ratio.
15. Stir the mixture thoroughly and place the mixture inside a vacuum jar for 30 minutes. This step removes any micro scale bubbles that can be trapped inside the mixture.
16. Slowly pour the PDMS mixture over Si/SU-8 substrate.
17. Cure the PDMS by placing the substrate inside 70° C. oven for 2 hours, as indicated in
18. Slowly peel off the PDMS, as indicated in
Transfer Printing Using Elastomeric Microtip Stamp
1. Prepare inks with desired material and dimensions, as shown in
2. Align microtip elastomeric stamp fabricated as described above with a target ink that will be transferred.
3. Apply a preload such that all microtips are fully collapsed resulting increased surface contact area, as indicated in
4. Rapidly retract the elastomeric microtip stamp for ink pick up, as indicated in
5. Transfer the ink to desired receiving site as indicated in
6. Contact the ink with the receiving site using marginal preload, as shown in
7. Raise the stamp slowly, as shown in
Blister Test Receiving Substrate Fabrication
I. Si Receiving Substrate, as Illustrated in
1. Deposit 200 nm of SiO2 using PECVD (PlasmaTherm) on Si wafer.
2. Pattern SiO2 layer to ring shape by photolithography, RIE etching (Axic), 40 sccm CF4, 200 W, 35 mTorr, 20 minutes), and photoresist stripping.
3. Pattern a 100 μm square via hole opening by photolithography, etch through the wafer by DRIE (STS Pegasus DRIE, C4F8 200 sccm, 100 mTorr, 2000 W coil power for 4 sec passivation step, SF6 450 sccm and O2 45 sccm, 100 mTorr, 2800 W coil power, 40 W platen power for 7 sec etch step), and strip photoresist.
4. Etch silicon using DRIE with oxide mask on (STS Pegasus DRIE).
5. Dip the silicon substrate into hydrofluoric acid to remove SiO2 mask.
6. Cleave the wafer into chips.
II. Au and SiO2 Receiving Substrates, as Illustrated in
1. Both Au and SiO2 begin with a Si receiving substrate prepared as described above.
2. For Au receiving sample, 400 nm Au is sputter (AJA ATC ORION 8HV) deposited (20 sccm Ar, 5×10−3 Torr, 300 W, 20 min for Au).
3. For SiO2 receiving substrate, the Si receiving substrate is placed inside furnace (Lindberg Hevi-Duty Lancer M-300) at 1100° C. with 6 sccm O2 for 24 hours to thermally grow 700 nm of SiO2.
III. SU-8 Receiving Substrate, as Illustrated in
1. Via hole is constructed using DRIE (STS Pegasus DRIE).
2. Spin coat SU8-50 (Microchem) at 3000 rpm and soft bake on hot plate for 65° C. for 6 minutes and 95° C. for 20 minutes.
3. Using i-line flood exposure UV lithography (Karl Suss MJB3 mask aligner), expose SU8-50 through a pattern mask for 200 mJ/cm2.
4. Post exposure bake at 65° C. for 1 minutes and 95° C. for 5 minutes.
5. Develop using SU-8 developer for 6-10 minutes (MicroChem).
Blister Test Specimen Assembly Via Micro-Lego
1. Prepare 3 μm thick, 900 μm diameter Si ink and microtip stamp following the procedures described above.
2. Bring the Si ink and the stamp together with high preload and rapidly raise the stamp to retrieve the Si disc ink, as shown in
3. Transfer the Si ink onto a receiving substrate prepared as described above, as shown in
4. Print the ink with precision, as indicated in
5. Thermally process the specimen for hermetic joining throughout the contact area, as shown in
Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible without departing from the present invention. The spirit and scope of the appended claims should not be limited, therefore, to the description of the preferred embodiments contained herein. All embodiments that come within the meaning of the claims, either literally or by equivalence, are intended to be embraced therein.
Furthermore, the advantages described above are not necessarily the only advantages of the invention, and it is not necessarily expected that all of the described advantages will be achieved with every embodiment of the invention.
The present patent document claims the benefit of priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 62/528,246, filed Jul. 3, 2017, which is hereby incorporated by reference in its entirety.
This invention was made with government support under contract number CMMI-1351370 awarded by the National Science Foundation. The government has certain rights in the invention.
Number | Name | Date | Kind |
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6245249 | Yamada | Jun 2001 | B1 |
8057891 | Cheng et al. | Nov 2011 | B2 |
8093340 | Xie et al. | Jan 2012 | B2 |
8236129 | Xie et al. | Aug 2012 | B2 |
8237324 | Pei et al. | Aug 2012 | B2 |
8251163 | Xie et al. | Aug 2012 | B2 |
8628838 | Xie et al. | Jan 2014 | B2 |
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20100123268 | Menard | May 2010 | A1 |
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Number | Date | Country | |
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20190006180 A1 | Jan 2019 | US |
Number | Date | Country | |
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62528246 | Jul 2017 | US |