Claims
- 1. A microcontroller comprising:
a central processing unit; a data memory having a linearized address space coupled with the central processing unit being divided into n banks; the central processing unit comprising:
a bank select unit which either accesses one of the banks or accesses a virtual bank, whereby the virtual bank combines partial memory space of two banks of the data memory and wherein the selected bank forms a register file; an arithmetic logic unit coupled with the register file; a plurality of special function registers being mapped to one of the banks in the data memory, wherein one of the special function registers is a working register being coupled with the arithmetic logic unit; a program counter register within the central processing unit, the program counter mapped in the data memory; and a working register within the central processing unit being coupled with the arithmetic logic unit, the working register mapped in the data memory; wherein the microcontroller having an instruction set for controlling the arithmetic logic unit and wherein at least one instruction comprises a bit indicating whether the bank select unit accesses one of the banks or the virtual bank.
- 2. A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 1110 1010 kkkk kkkk, wherein upon invocation of the instruction, an 8 bit literal is copied to the location pointed to by a file select register, and the file select register is then decremented, the literal ‘k’ is designated in the kkkk kkkk portion of the instruction.
- 3. A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 1110 1001 ffkk kkkk, wherein upon invocation of the instruction, a 6 bit unsigned literal is subtracted from a file select register to form a result, the result being stored into the file select register, the literal being designated in the kk kkkk portion of the instruction, the file select register begin designated in the ff portion of the instruction.
- 4. A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 1110 1001 11kk kkkk, wherein upon invocation of the instruction, an unsigned 6 big literal is subtracted from a file select register to form a result, the result being stored back into the file select register and returned, the literal being designated in the kk kkkk portion of the instruction.
- 5. A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 1110 1000 ffkk kkkk, wherein upon invocation of the instruction, an unsigned 6 bit literal is added to a file select register, the result being stored into the file select register, the literal being designated in the kk kkkk portion of the instruction, the file select register being designated in the ff portion of the instruction.
- 6 A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 1110 1000 11kk kkkk, wherein upon invocation of the instruction, a 6 bit literal designated by the kk kkkk portion of the instruction is added to a file select register and the result is stored back into the file select register.
- 7. A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 1110 1011 0sss ssss 1111 dddd dddd dddd, wherein upon invocation of the instruction, an 8 bit value is copied to a destination designated by the 12 bit value dddd dddd dddd, the location of the 8 bit value that is copied to the destination is designated by adding the 7 bit literal value sss ssss to the value in a file select register.
- 8. A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 1110 1011 1sss ssss 1111 xxxx xddd dddd, wherein upon invocation of the instruction, an 8 bit value is copied to a location designated by ddd dddd portion of the instruction, the location of the 8 bit value is determined by adding the 7 bit literal value sss ssss to the value in a file select register.
- 9. A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 0000 0000 0001 0100, wherein upon invocation of the instruction, an address of a next instruction is pushed onto a hardware stack.
- 10. A microcontroller as in claim 1 wherein the instruction set includes an instruction with an encoding of 0000 0000 0001 0100, wherein upon invocation of the instruction, the values from a first register are copied into an upper 16 bits of a program counter and a value in a second register are copied into a lower 8 bits of the program register.
- 11. A microcontroller comprising:
a central processing unit; a data memory coupled with the central processing unit being divided into n banks; the central processing unit comprising:
a bank select unit for selecting one of the banks in the data memory, wherein the selected bank forms a register file; an arithmetic logic unit coupled with the register file; and a plurality of special function registers being mapped to one of the banks in the data memory; wherein one of the special function registers is a working register being coupled with the arithmetic logic unit.
- 12. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 1110 1010 kkkk kkkk, wherein upon invocation of the instruction, an 8 bit literal is copied to the location pointed to by a file select register, and the file select register is then decremented, the literal ‘k’ is designated in the kkkk kkkk portion of the instruction.
- 13. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 1110 1001 ffkk kkkk, wherein upon invocation of the instruction, a 6 bit unsigned literal is subtracted from a file select register to form a result, the result being stored into the file select register, the literal being designated in the kk kkkk portion of the instruction, the file select register begin designated in the ff portion of the instruction.
- 14. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 1110 10011 11kk kkkk, wherein upon invocation of the instruction, an unsigned 6 big literal is subtracted from a file select register to form a result, the result being stored back into the file select register and returned, the literal being designated in the kk kkkk portion of the instruction.
- 15. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 1110 1000 ffkk kkkk, wherein upon invocation of the instruction, an unsigned 6 bit literal is added to a file select registered, the result being stored into the file select register, the literal being designated in the kk kkkk portion of the instruction, the file select register being designated in the ff portion of the instruction.
- 16. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 1110 1000 11kk kkkk, wherein upon invocation of the instruction, a 6 bit literal designated by the kk kkkk portion of the instruction is added to a file select register and the result is stored back into the file select register.
- 17. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 1110 1011 0sss ssss 1111 dddd dddd dddd, wherein upon invocation of the instruction, an 8 bit value is copied to a destination designated by the 12 bit value dddd dddd dddd, the location of the 8 bit value that is copied to the destination is designated by adding the 7 bit literal value sss ssss to the value in a file select register.
- 18. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 1110 1011 1sss ssss 1111 xxxx xddd dddd, wherein upon invocation of the instruction, an 8 bit value is copied to a location designated by ddd dddd portion of the instruction, the location of the 8 bit value is determined by adding the 7 bit literal value sss ssss to the value in a file select register.
- 19. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 0000 0000 0001 0100, wherein upon invocation of the instruction, an address of a next instruction is pushed onto a hardware stack.
- 20. A microcontroller as in claim 11 wherein the instruction set includes an instruction with an encoding of 0000 0000 0001 0100, wherein upon invocation of the instruction, the values from a first register are copied into an upper 16 bits of a program counter and a value in a second register are copied into a lower 8 bits of the program register.
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation-in-part of U.S. Ser. No. 09/280,112 that was filed on Mar. 26, 1999 by the same title and to the same inventors as the present application. This application is related to the following applications: U.S. Pat. No. 6,055,211 for “FORCE PAGE ZERO PAGING SCHEME FOR MICROCONTROLLERS USING DATA ACCESS MEMORY” by Randy L. Yach, et al.; U.S. Pat. No. 5,905,880 for “ROBUST MULTIPLE WORK INSTRUCTION AND METHOD THEREFOR” by Rodney J. Drake, et al.; U.S. Pat. No. 6,192,463 for “PROCESSOR ARCHITECTURE SCHEME WHICH USES VIRTUAL ADDRESS REGISTERS TO IMPLEMENT DIFFERENT ADDRESSING MODES AND METHOD THEREFOR” by Sumit Mitra, et al.; U.S. Pat. No. 6,243,798 for “COMPUTER SYSTEM FOR ALLOWING A TWO WORD INSTRUCTION TO BE EXECUTED IN THE SAME NUMBER OF CYCLES AS A SINGLE WORD JUMP INSTRUCTION” by Rodney J. Drake, et al.; U.S. Pat. No. 6,029,241 entitled “PROCESSOR ARCHITECTURE SCHEME HAVING MULTIPLE BANK ADDRESS OVERRIDE SOURCES FOR SUPPLYING ADDRESS VALUES AND METHOD THEREFORE” by Igor Wojewoda, Sumit Mitra, and Rodney J. Drake; U.S. Pat. No. 6,098,160 for “DATA POINTER FOR OUTPUTTING INDIRECT ADDRESSING MODE ADDRESSES WITHIN A SINGLE CYCLE AND METHOD THEREFOR” by Rodney J. Drake, et al.; U.S. Pat. No. 5,958,039 for “MASTER-SLAVE LATCHES AND POST INCREMENT/DECREMENT OPERATION” by Allen, et al.; and U.S. Pat. No. 5,987,583 for “PROCESSOR ARCHITECTURE SCHEME AND INSTRUCTION SET FOR MAXIMIZING AVAILABLE OPCODES AND ADDRESSING SELECTION MODES” by Triece, et al. which are hereby incorporated herein by reference for all purposes.
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
09280112 |
Mar 1999 |
US |
Child |
10796771 |
Mar 2004 |
US |