The present invention relates broadly to a micromechanical structure and to a method of fabricating a micromechanical structure.
In current semiconductor manufacturing technology, wide bandgap materials are typically used in optoelectronic and microelectronic devices. One such material is Gallium Nitride (GaN). GaN typically has properties such as a wide bandgap (e.g. Eg ˜3.4 eV at 300K), a large elastic modulus, high piezoelectric and piezoresistive coefficients and chemical inertness. Thus, GaN is a suitable material for microelectromechanical systems (MEMS) applications, more particularly in harsh conditions such as conditions requiring high-temperature piezoelectrics and high breakdown voltages etc.
Typically, due to the lack of GaN single crystals, GaN heteroepitaxial layers for optoelectronics and microelectronics device applications are grown on “foreign” substrates such as on sapphire (α-Al2O3) substrates having about 16% lattice mismatch, or on silicon carbide (SiC) substrates having about 3.4% lattice mismatch. It has been shown that these “foreign” substrates are typically not desirable. For example, as-grown GaN films on sapphire substrates have been shown to contain a high density of defects (e.g. mainly threading dislocations) due to the substantial lattice mismatch and thermal expansion coefficient difference between the GaN epilayers and the substrates.
Progressing from “foreign” substrates, there are other substrates, for example, silicon (Si) or silicon-on-insulator (SOI) substrates that can be used for the heteroepitaxial growth of GaN. Growth of GaN on Si (111) substrates may potentially provide an option of using silicon as a less expensive or more accessible alternative to traditional substrates. Potentially, GaN-based devices may be integrated on well-established silicon process technology. However, due to the large differences in lattice constants and thermal expansion coefficients, good quality GaN films on Si substrates cannot be obtained by metalorganic chemical vapor deposition (MOCVD). It has been proposed to use different buffer layers or intermediate layers, such as AlN and Al0.27Ga0.73N/AlN layers, to improve the GaN quality on Si. The large difference in the lattice and thermal mismatch can be avoided if suitable growth conditions are used. Apart from high-temperature AlN buffers, the method by Wang et al. described in “Effects of periodic delta-doping on the properties of GaN:Si films grown on Si(111) substrates” Appl. Phys. Lett. 85, 5881 (2004), uses suitable Si-delta-doped interlayers to reduce the cracks and tensile stress.
The integration of GaN-based devices to Si electronics can be possible if good quality wurtzite GaN epilayers can be grown on Si (100) or SOI substrates. Zhou et al, in “Comparison of the properties of GaN grown on complex Si-based structures”, Appl. Phys. Lett., 86, 081912 2005, describe GaN growth on SOI (111) that is related to integration. SOI-based technology is typically being used in microscale applications that include electronic and microelectromechanical system (MEMS) devices where single crystal silicon can offer advantages such as process control and providing reliable electronic and mechanical properties. SOI wafers can typically be prepared using methods such as wafer bonding, Smart-cut processes and the so-called Separation by Implantation of Oxygen (SIMOX) method. Using SOI substrates can provide some advantages over using sapphire or SiC substrates. The advantages include the availability of large size substrates (e.g. up to 12 in.), relatively lower cost, and easier integration with Si-based microelectronics.
M. A. Shah, S. Vicknesh, L. S. Wang, J. Arokiaraj, A. Ramam, S. J. Chua and S. Tripathy, “Fabrication of Freestanding GaN Micromechanical Structures on Silicon-on-Insulator Substrates”, Electrochem. Solid-State Lett., 8, G275 2005 describe the growth of GaN-based epilayers on (100) oriented SOI substrates prepared by the SIMOX method using MOCVD and the fabrication processes to realize GaN based micromechanical structures on a SOI platform. L. S. Wang, S. Tripathy, S. J. Chua and K. Y. Zang, “InGaN/GaN multi-quantum-well structures on (111)-oriented bonded silicon-on-insulator substrates”, Appl. Phys. Lett., 87 111908 2005 describe the growth of InGaN/GaN multiple quantum wells (MQWs) with sharp interfaces on (111)-oriented bonded SOI substrates.
One problem that may arise during development of GaN-based MEMS is a lack of efficient sacrificial etchants. Publications such as R. P. Strittmatter, R. A. Beach, T. C. McGill, “Fabrication of GaN suspended microstructures”, Appl. Phys. Lett., 78 3226 2001 and A. R. Stonas, N. C. MacDonald, K. L. Turner, S. P. DenBaars, E. L. Hu, “Photoelectrochemical undercut etching for fabrication of GaN microelectromechanical systems”, J. Vac. Sci. Technol., B 19 2838 2001 and A. R. Stonas, P. Kozodoy, H. Marchand, P. Fini, S. P. DenBaars, U. K. Mishra and E. L. Hu, “Backside-illuminated photoelectrochemical etching for the fabrication of deeply undercut GaN structures”, Appl. Phys. Lett., 77 2610 2000 describe fabrication processes of III-nitrides-based MEMS using chemical etching.
In publications such as S. Davies, T. S. Huang, M. H. Gass, A. J. Papworth, T. B. Joyce, P. R. Chalker, “Fabrication of GaN cantilevers on silicon substrates for microelectromechanical devices”, Appl. Phys. Lett., 8425562004, S. Davies, T. S. Huang, R. T. Murray, M. H. Gass, A. J. Papworth, T. B. Joyce, P. R. Chalker, “Fabrication of epitaxial III-nitride cantilevers on silicon (111) substrates”, J. Mat. Sci., 15 705 2004, Z. Yang, R. N. Wang, S. Jia, D. Wang, B. S. Zhang, K. M. Lau, and K. J. Chen, “Mechanical characterization of suspended GaN microstructures fabricated by GaN-on-patterned-silicon technique”, Appl. Phys. Lett., 88, 041913 2006 and Z. Yang, R. Wang, D. Wang, B. Zhang, K. M. Lau, K. J. Chen, “GaN-on-patterned-silicon (GPS) technique for fabrication of GaN-based MEMS”, Sensors and Actuators A, Accepted for Publication (Inpress), combined dry and wet chemical etching steps have been described to realize GaN surface micromachined microstructures on Si(111) substrates. However, one disadvantage with using a wet chemical for sacrificial etching is the released microstructures must be dried in a way so as to prevent the microstructures from collapsing due to meniscus forces (stiction).
That is, the typical process to obtain free-standing surface-micromachined structures is to rinse the wet chemical etchant used to free the structures with deionized (DI) water and dry the structures using evaporation. Using this process, a flexible microstructure can be pulled down to the substrate by the capillary force of water droplets in e.g. the airgap and may remain stuck to the substrate even after the microstructure is completely dried. Studies have shown that factors such as solid bridging, van der Waals forces and electrostatic forces can give rise to stiction.
In addition to GaN, another material that is suitable for use in photonic and electronic applications is Zinc Oxide (ZnO). ZnO is typically used in a wide range of applications such as in semiconducting, photoconducting, piezoelectric sensors and optical waveguides. ZnO has a number of unique properties such as having a direct wide band gap (e.g. Eg ˜3.3 eV at 300K) and a large exciton binding energy (˜60 meV). Typically, ZnO is used for semiconductor devices operating in harsh environments, such as in space and nuclear reactors, because it is more radiation-resistive than materials such as Si, GaAs, SiC, or GaN.
For using ZnO for MEMS applications, one problem that may arise is ZnO material is easily etched by wet chemical etchants that are typically used for sacrificial etching. Thus, to realize ZnO MEMS, it is desirable to develop a dry-releasing technique.
Further to the above, yet other alternative materials for developing MEMS for use in harsh environments include microcrystalline and nanocrystalline diamond (NCD). Such materials have significant mechanical strength, chemical inertness, thermal stability and tribological performance. Freestanding NCD-mechanical structures are typically fabricated using SiO2 as a sacrificial layer. However, the SiO2 sacrificial layer is typically removed using hydrofluoric (HF) wet and/or gas etch. One disadvantage with wet chemical for sacrificial etching is the released diamond microstructures must be dried in such a way so as to prevent the structures from collapsing due to meniscus forces. This is the stiction discussed above.
Therefore, to realize e.g. wide bandgap ultra-nanocrystalline and microcrystalline diamond micromechanical structures and/or for realizing surface micromachined GaN and ZnO microstructures without stiction related problems, a dry release technique is desired.
For etching silicon, gas phase pulse etching using Xenon Difluoride (XeF2) has been used as a silicon etchant. XeF2 is a member of a family of fluorine-based silicon etchants which includes ClF3, BrF3, BrF5, and IF5. High etch rates and reaction probabilities at room temperature were found when XeF2 vapor was first used to study the mechanisms of fluorine etch chemistry on silicon. As a silicon etchant, XeF2 has unique properties such as an ability to etch without excitation or external energy sources thus exhibiting a high selectivity to many metals, dielectrics and polymers used in traditional integrated circuit fabrication, providing isotropic etching, and providing gentle dry reaction etching. XeF2 is a white solid material at room temperature and at atmospheric pressure. In a vacuum environment, solid XeF2 instantly sublimates and isotropically etches silicon without physical excitation.
Hoffman et al. in “3D structures with piezoresistive sensors in standard CMOS,” Proceedings of Micro Electro Mechanical Systems Workshop (MEMS '95), 288 1995 describe creating 3-dimensional structures with piezoresistive sensors in a standard CMOS process using XeF2 to bulk micromachine the chips. Further, U.S. Pat. No. 7,041,224B2, U.S. Pat. No. 6,942,811B2, U.S. Pat. No. 6,960,305 and U.S. Pat. No. 7,027,200B2 describe apparatus improvements (e.g. to accurately determine the end-point of the etch step) and methods used in etching of sacrificial silicon layers for a micromechanical structure (e.g. a micromirror array for a projection display and silicon-based deflectable MEMS elements) by the use of gas phase etchants, particularly in the absence of plasma (such as XeF2 with one or more diluents). Thus, silicon can be preferentially etched with respect to non-silicon materials, which include titanium, gold, aluminum, and compounds of these metals as well as silicon carbide, silicon nitride, photoresists, polyimides, and silicon oxides. Jang et al. in US20030193269A1 describe a method of forming a film bulk acoustic resonator (FBAR) having an activation area resonating with a predetermined frequency signal. The method includes forming a poly silicon layer as the sacrificial layer followed by removing the sacrificial layer using XeF2 to form a corresponding air-gap. The method further includes forming a thin layer made of dielectric material, such as AlN or ZnO, on a semiconductor substrate, such as silicon or GaAs, to generate a resonance using a piezoelectric characteristic of the thin layer.
In the above publications, for using XeF2 for dry etching, a sacrificial layer is typically deposited and patterned as additional process steps so that an airgap may be formed after the XeF2 dry etching. However, depositing and patterning of the sacrificial layer can give rise to increased complexity in the fabrication process and may incur additional cost.
Hence, there exists a need for a micromechanical structure and a method of fabricating a micromechanical structure that seek to address at least one of the above problems.
In accordance with an aspect of the present invention, there is provided a micromechanical structure comprising a silicon (Si) based substrate; a micromechanical element formed directly on the substrate; and an undercut formed underneath a released portion of the micromechanical element; wherein the undercut is in the form of a recess formed in the Si based substrate.
The Si based substrate may comprise a silicon-on-insulator (SOI) substrate.
A thickness of a Si overlayer of the SOI substrate may be chosen for controlling a stress in the released portion of the micromechanical element.
The recess may extend through substantially the thickness of the Si overlayer of the SOI substrate.
The thickness may be in a range of about 10 nm to about 10 μm.
The SOI substrate may be provided using wafer bonding, Separation by Implantation of Oxygen (SIMOX) or both.
A crystalline orientation of the SOI substrate may be chosen for controlling the stress in the released portion of the micromechanical element.
The crystalline orientation may be (100) or (111).
The Si based substrate may comprise a bulk Si substrate.
The bulk Si substrate may comprise a crystalline orientation of (100) or (111).
The micromechanical element may comprise one or more materials selected from a group consisting ZnO, Zn(Mg)O, Zn(Cd)O, ZnS, GaN, AlN, AlGaN, InGaN, InN, polycrystalline diamond and nanocrystalline diamond.
The recess may be formed in the Si based substrate using a dry etch process.
The dry etch process may comprise usage of XeF2.
The micromechanical element may comprise an optoelectronic device.
The micromechanical element may comprise a microelectronic device.
The optoelectronic device may comprise a light emitting diode (LED).
The microelectronic device may comprise one or more Field-effect transistors (FETs).
In accordance with another aspect of the present invention, there is provided a method of fabricating a micromechanical structure, the method comprising the steps of providing a silicon (Si) based substrate; forming a micromechanical element directly on the substrate; forming an undercut in the form of a recess underneath a released portion of the micromechanical element; and forming the recess in the Si based substrate.
The Si based substrate may comprise a silicon-on-insulator (SOI) substrate.
The method may further comprise choosing a thickness of a Si overlayer of the SOI substrate for controlling a stress in the released portion of the micromechanical element.
The recess may extend through substantially the thickness of the Si overlayer of the SOI substrate.
The thickness may be in a range of about 10 nm to about 10 μm.
The Si based substrate may be provided using wafer bonding, Separation by Implantation of Oxygen (SIMOX) or both.
The method may further comprise choosing a crystalline orientation of the SOI substrate for controlling the stress in the released portion of the micromechanical element.
The crystalline orientation may be (100) or (111).
The Si based substrate may comprise a bulk Si substrate.
The bulk Si substrate may comprise a crystalline orientation of (100) or (111).
The micromechanical element may comprise one or more materials selected from a group consisting ZnO, Zn(Mg)O, Zn(Cd)O, ZnS, GaN, AlN, AlGaN, InGaN, InN polycrystalline diamond and nanocrystalline diamond.
The forming an undercut in the form of a recess may comprise using a dry etch process.
The dry etch process may comprise using XeF2.
The micromechanical element may comprise an optoelectronic device.
The micromechanical element may comprise a microelectronic device.
The optoelectronic device may comprise a light emitting diode (LED).
The microelectronic device may comprise one or more Field-effect transistors (FETs).
Embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:
a) is a schematic diagram illustrating a sample comprising a Gallium Nitride (GaN) layer formed on a Separation by Implantation of Oxygen silicon-on-insulator (SIMOX_SOI) (100) substrate in an example embodiment.
b) is an intensity vs Raman shift graph showing a micro-Raman spectrum measured for the GaN layer.
c) is a photoluminescence (PL) intensity vs wavelength graph showing a PL spectrum measured for the GaN layer.
a) to (c) are microscope images showing the sample after Xenon Difluoride (XeF2) etching at progressive time intervals of 45 delta T.
d) is an intensity vs Raman shift graph showing measured micro-Raman spectra of the sample of
a) is a microscope image of a sample with a larger membrane size in another example embodiment.
b) is an intensity vs Raman shift graphs showing a measured micro-Raman spectra of the sample of
c) is a Scanning Electron Microscope (SEM) image showing an airgap under a sample GaN cantilever structure on the SIMOX SOI(100) substrate of
d) is a SEM image showing an airgap under sample GaN beams attached to freestanding membranes on a sample SIMOX SOI(100) platform.
a) is an E2 phonon peak intensity mapping diagram of the sample of
b) is a Raman stress profile mapping diagram of the sample of
a) is a schematic diagram illustrating a sample comprising a GaN epilayer having a high-temperature aluminium nitride (AlN) buffer layer grown on a Si(111) substrate in an example embodiment.
b) is a PL intensity vs bandgap energy graph showing a PL spectrum of the sample of
a) is a scanning electron microscope (SEM) image of a released GaN structure of the sample of
b) is an intensity vs Raman shift graph showing a micro-Raman spectrum measured for the GaN structure of
c) is an E2 phonon peak intensity mapping diagram of the GaN structure of
d) is a Raman stress profile mapping diagram of the GaN structure of
a) is a SEM image showing freestanding GaN cantilever structures of the sample of
b) is an E2 phonon peak intensity mapping diagram of the GaN cantilever structures of the sample of
c) is a Raman stress profile mapping diagram of the GaN cantilever structures of the sample of
a) is a schematic diagram illustrating a sample in another example embodiment.
b) is a PL intensity vs wavelength graph showing temperature-dependent micro-PL measurements performed between 77K and 350K on the sample of
c) is a PL intensity vs wavelength graph showing room temperature PL spectrum measurements on the ZnO layer.
d) is a cross-sectional SEM image of the sample of
a) is a microscope image of a cantilever structure of the sample of
b) is a microscope image of the cantilever structure of the sample of
a) is a schematic diagram illustrating a sample in an example embodiment.
b) is a PL intensity vs wavelength graph showing PL spectra measured from the sample of
a) is a microscope image showing a ZnO bridge structure of the sample of
b) is a microscope image showing cantilever structures of the sample of
a) is a SEM image of a released ZnO bridge structure of the sample of
b) is a SEM image of cantilever structures of the sample of
a) is an intensity vs Raman shift graph showing measured micro-Raman spectra of the bridge structure of
b) is an intensity vs Raman shift graph showing measured micro-Raman spectra of the cantilever structures of
c) is a Raman mapping diagram of E2 phonon intensity in the ZnO micro-bridge structure of
a) is a SEM image of a released ZnO bridge structure on bulk Si(111) platforms in another example embodiment.
b) is a SEM image of cantilever structures on a bulk Si(111) platform in the example embodiment.
a) is a SEM image of freestanding nanocrystalline diamond (NCD) cantilever structures in an example embodiment.
b) is a SEM image of a freestanding NCD bridge structure in the example embodiment.
a) is a cross section SEM image showing chemical vapour deposition (CVD)-grown microcrystalline diamond mechanical structures in another example embodiment.
b) is a SEM image showing polycrystalline/microcrystalline diamond cantilevers in the example embodiment.
c) is a SEM image showing polycrystalline/microcrystalline micro-bridge structures in the example embodiment.
a) is an optical microscope image showing a light emitting diode (LED) microstructure on a bulk silicon platform in another example embodiment.
b) is an optical microscope image showing field effect transistor (FET) cantilevers on a bulk silicon platform in the example embodiment.
c) is an optical microscope image showing a LED microstructure on a SOI platform in the example embodiment.
d) is an optical microscope image showing FET cantilevers on a SOI platform in the example embodiment.
a) is an optical microscopic image of microdisk LED structures in yet another example embodiment.
b) is a SEM image of the microdisk LED structures in the example embodiment.
c) is an electroluminescence (EL) intensity vs wavelength graph showing an EL spectrum measured from the microdisk LED structures in the example embodiment.
Example embodiments described below can provide surface micro-machined wide bandgap nano/micromechanical structures (e.g. comprising ZnO, GaN, and nanocrystalline diamond) grown directly on Si and/or SOI substrates using a dry releasing technique. The dry releasing technique employed in the example embodiments is a controlled gas phase pulse etching with Xenon Difluoride (XeF2) which can selectively etch Si and SOI overlayers inherent to the Si and/or SOI substrates, thus undercutting the wide bandgap material. In the example embodiments, the dry releasing technique is used to etch a “sacrificial layer” of Si or Si overlayers inherent to the Si and/or SOI substrates, thus creating an airgap for any wide bandgap materials grown on top of the Si and/or SOI substrates. Thus, in example embodiments, there is no requirement for depositing and patterning an additional, dedicated sacrificial layer. On the other hand, control of the thickness of the airgap can be maintained in example embodiments by providing e.g. SOI substrates with a chosen Si overlayer thickness. In other words, in such embodiments, the control of the airgap thickness is advantageously separated from the device buildup processes, e.g. depositing GaN, ZnO, NCD materials etc. onto the substrates, and rather is incorporated into the pre-fabrication of SOI wafers by a simple control of silicon thickness in e.g. well-established SOI formation techniques such as wafer bonding, SIMOX etc.
For control of the silicon thickness using SIMOX, reference is made to publications M. Bruel, “Silicon on insulator material technology”, Electron. Lett., 31, 1201 1995, M. Bruel, B. Aspar, and A. J. Auberton-Hervé, “Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding”, Jpn. J. Appl. Phys., Part 1, 36, 1636 1997 and O. W. Holland, D. Fathy, and D. K. Sadana, “Formation of ultrathin, buried oxides in Si by O+ ion implantation”, Appl. Phys. Lett., 69, 674 1996.
As the thickness of the silicon overlayer is controlled during substrate fabrication, the thickness of the airgap formed can be controlled. Thus, residual stress of the wide bandgap materials can be controlled by designing the silicon overlayer inherent to the substrates below the wide bandgap materials. In such example embodiments, as XeF2 is highly selective to dielectrics, the XeF2 selectively etches the silicon overlayers inherent to the substrates to form corresponding airgaps. It will be appreciated that the XeF2 does not etch underlying SiO2 below the silicon overlayers of the SOI substrates. Thus, the SiO2 layer of a SOI substrate functions as an inherent etch stop.
In the following description, sample preparation/formation for the example embodiments and characterization techniques are briefly introduced before the example embodiments are described in more detail.
For some example embodiments, GaN-based epilayers are grown on commercially obtained (100) and (111) oriented SOI substrates fabricated by the SIMOX method using MOCVD. Such substrates can provide a buried oxide layer of about 150-350 nm thickness and a Si overlayer of about 50-200 nm. In one sample, a GaN layer with a thin AlN buffer is grown on a Si (111) substrate to highlight the potential of the dry releasing technique for fabrication of GaN micromechanical structures directly on bulk Si (111). In such example embodiments, the GaN layers grown on bulk silicon (111) and SOI substrates are subjected to periodic delta doping to reduce cracks and tensile stress. It will be appreciated that growing the layers on e.g. AlN buffers and using periodic delta doping steps during MOCVD epitaxy can produce good GaN epitaxy on Si(111). Such growth methods can also be applied to SIMOX SOI(111) and SOI(100) substrates. In addition, for some example embodiments, to demonstrate using other wide bandgap materials, ZnO material is deposited/grown e.g. by RF magnetron sputtering on (111) oriented SOI substrates fabricated by the SIMOX method and on wafer bonded SOI substrates. In some samples, the buried oxide layers range from about 370 nm to 2.0 μm thickness and the Si overlayers range from about 200 nm to 3.0 μm.
The ZnO and GaN samples are characterized by optical techniques such as micro-photoluminescence (PL) and micro-Raman measurements.
For some example embodiments, ultra-nanocrystalline diamond (UNCD) films of about 2.0 μm thick are grown on Si-based substrates by microwave plasma chemical vapor deposition techniques. These films can show ultra smooth diamond morphology and the nature of the crystalline quality can be studied by micro-Raman spectroscopy.
The samples described above are diced into 2×2 cm samples. The samples are cleaned in a Class 100 cleanroom using Acetone and Methanol in an ultrasonic bath for a period of about 5 minutes for each solvent. Thereafter, the samples are rinsed under DI water, blow dried with N2 gas and pre-baked in an oven (e.g. Memmert) at about 90° C. for about 10 minutes. After heating, the samples are spin-coated using a Spincoater (e.g. Model CEE 100 from Brewer Science, INC.) with AZ4330 photoresist (PR) at about 5000 rpm for about 30 seconds. The samples are then placed in an oven for soft baking at about 90° C. for about 30 minutes. Photolithography is then performed using a Karl Suss Mask Aligner (MA8) I-line, with ultraviolet light (about 365 nm) with an intensity of approximately 4.5-5 mW. In the example embodiments, 3″ mask plates with features of different membrane, cantilever and bridge dimensions are used for patterning. After the photolithography, before etching, the photoresist thicknesses were measured to be approximately 3 μm on the patterned samples.
For etching, the samples are etched in a load-locked Unaxis SLR 770 high-density plasma etch system consisting of an inductive coupled plasma (ICP) chamber (operating at about 2 MHz) and an additional RF bias (about 13.56 MHz) for the sample chuck. Helium backside cooling is incorporated to allow the temperature of the sample substrates to be more effectively controlled. The samples are mounted on an 8-in.-Si carrier wafer with vacuum grease before they are introduced in the etching chamber. Boron Trichloride (BCl3) and Chlorine (Cl2) gases of purity 99.999% are introduced for structural etching. The samples are etched in the ICP chamber for a duration of time, depending on the type of wide bandgap material, using constant process parameters of about 20 sccm BCl3 flow, 10 sccm Cl2 flow, 500 W ICP power, 200 W Reactive Ion Etching (RIE) power, 5 mTorr pressure and 6° C. temperature.
After etching, etch depths of the remaining material and photoresist are determined by using a KLA Tencor P-10 Surface Profiler. Photoresist is stripped off using acetone and step heights of the etched material are measured again using the surface profiler. This is to ascertain the exposure conditions of underlying layers (inherent to the substrates) below the wide bandgap materials for a subsequent sacrificial layer etching. For the samples, releasing the respective wide bandgap material is achieved by sacrificial etching of the respective substrate Si overlayer using XeF2 in a customized Penta Vacuum System. Images of the released wide bandgap structures are captured in a secondary electron imaging (SEI) mode using a JEOL JSM 5600 scanning electron microscope (SEM) equipped with a resolution of about 3.5 nm and accelerating voltage in the range 5 kV-10 kV.
Further, the released samples are characterized by spatially resolved Raman scattering in the back scattering geometry at room temperature. The 514.5 nm line of an argon ion laser is used for the Raman scattering measurement. The scattered light is dispersed through a JY-T64000 triple monochromator system attached to a liquid nitrogen cooled charge coupled device (CCD) detector. The accuracy of the Raman measurements is about 0.2 cm−1 with a lateral spatial resolution of about 1.2 μm. The samples are subjected to excitation perpendicular to the substrates and the back scattering light is detected by the same objective used to focus the incident laser light.
After the brief introduction of the sample preparation/formation and characterization techniques, the example embodiments are described in more detail in the following description.
a) is a schematic diagram illustrating a sample 100 comprising a GaN layer 102 formed on a SIMOX_SOI (100) substrate 104 in an example embodiment. The GaN layer 102 of about 1.5 to 1.7 μm is formed directly on the substrate 104 without depositing an additional or “dedicated” sacrificial layer. The substrate 104 inherently comprises an “inherent” Si overlayer 106 of about 200 nm thickness and an “inherent” buried oxide layer 108 of about 350 nm thickness. The sample 100 is patterned with features of different membrane sizes using standard photolithography and is etched for a period of about 11 mins to a depth of about 2 μm using constant process parameters of about 20 sccm BCl3 flow, 10 sccm Cl2 flow, 500 W ICP power, 200 W RIE power, 5 mTorr pressure and 6° C. temperature.
Thus, it will be appreciated that the control of airgap thickness is advantageously separated from the device buildup processes and is provided by a control of the “inherent” Si overlayer thickness.
b) is an intensity vs Raman shift graph showing the micro-Raman spectrum measured for the GaN layer 102.
The sample 100 is then subjected to XeF2 etching of the Si overlayer 106 using a single pulse of progressive timings.
For the measurements of
Although the etching of Si with XeF2 is highly selective, it is also time dependent.
b) is an intensity vs Raman shift graph showing the measured micro-Raman spectra. The platform 302 is measured first followed by the membrane 304 and the released beam 306. From the spectra, it can be observed that the platform 302 has a strong Si intensity at 520 cm−1 (see numeral 310) while the E2 phonon intensity has a weak signal at 565.9 cm−1 (see numeral 312). The unreleased membrane 304 has a moderately weak Si intensity at 520 cm−1 (see numeral 314) and the weakest E2 phonon intensity of GaN at 566.9 cm−1 (see numeral 316). However, the released beam 306 has the strongest E2 phonon intensity at 567.3 cm−1 (see numeral 318) and the weakest Si intensity at 520 cm−1 (see numeral 320). The E2 phonon line of GaN on SOI substrate (ie the platform 302) is lower as compared to E2 phonon line of the released beam 306. However, the E2 phonon line of the unreleased GaN membrane 304 is similar to that of the released beam 306, indicating that the membrane 304 is approaching strain free but the presence of Si peak (see numeral 314) indicates that it is not completely released from the Si overlayer (not shown). It will be appreciated that a longer duration of XeF2 etching can release the membrane 304.
In the above example embodiments, cross-section SEM can be used to study the released membrane and cantilever structures respectively of the sample 100 shown in
c) is a SEM image showing an airgap under a sample GaN cantilever structure on the SIMOX SOI(100) substrate 104.
a) is a E2 phonon peak intensity mapping diagram of the sample 100 of
In another example embodiment, a similar XeF2 dry-etching process and characterization is carried out for a GaN/SOI (111) platform.
In yet another example embodiment, surface micromachining is performed on a GaN layer formed directly on a bulk Si(111) substrate without depositing an additional or “dedicated” sacrificial layer. This can demonstrate the feasibility of using dry etching for creating large airgaps and can be for checking mechanical stability of freestanding GaN membranes and cantilevers formed after the dry etching.
a) is a schematic diagram illustrating a sample 500 comprising a GaN epilayer 502 having a high-temperature AlN buffer layer grown on a Si(111) substrate 504 in the example embodiment. The GaN epilayer 502 has a thickness of about 1.7 μm.
The sample 500 is patterned with features of different membrane sizes using standard photolithography and is etched for a period of about 9 mins to a depth of about 2.5 μm using constant process parameters of about 20 sccm BCl3 flow, 10 sccm Cl2 flow, 500 W ICP power, 200 W RIE power, 5 mTorr pressure and 6° C. temperature. Subsequently, the sample 500 is subjected to XeF2 etching of the Si handle wafer for a single pulse of progressive timings.
Microscope images of the sample 500 etched using XeF2 for progressive timings show a change in the contrast of a membrane of the sample 500, indicating the presence of an airgap (compare
From
c) is an E2 phonon peak intensity mapping diagram of the GaN structure 602 of
a) is a SEM image 700 showing freestanding GaN cantilever structures e.g. 702, 704 of the sample 500 (
b) is an E2 phonon peak intensity mapping diagram of the GaN cantilever structures e.g. 702, 704 of the sample 500 (
In another example embodiment, using a conventional RF Magnetron system, ZnO material of about 500-600 nm thickness is sputtered directly onto SIMOX_SOI (111) wafers.
a) is a schematic diagram illustrating a sample 800 in the example embodiment. The sample 800 comprises a SIMOX_SOI (111) substrate 802 that includes an “inherent” SiO2 layer 804 of about 370 nm thickness and an “inherent” Si overlayer 806 of about 200 nm thickness. The sample 800 further comprises a ZnO layer 808 of about 600 nm sputtered on the SIMOX_SOI (111) substrate 802 (ie. on the Si overlayer 806), without depositing an additional or “dedicated” sacrificial layer.
Thus, it will be appreciated that the control of airgap thickness is advantageously separated from the device buildup processes and is provided by a control of the “inherent” Si overlayer thickness.
b) is a PL intensity vs wavelength graph showing temperature-dependent micro-PL measurements performed between 77K and 350K on the ZnO layer 808 sputtered on the SIMOX_SOI substrate 802. From
c) is a PL intensity vs wavelength graph showing room temperature PL spectrum measurements on the ZnO layer 808 sputtered on the Si overlayer 806.
In the example embodiment, the ZnO layer 808 is patterned with features of varying bridges and cantilever lengths using standard photolithography and etched for a period of about 10 mins to a depth of about 620 nm using constant process parameters of about 20 sccm BCl3 flow, 10 sccm Cl2 flow, 500 W ICP power, 200 W RIE power, 5 mTorr pressure and 6° C. temperature. The sample 800 is subjected to XeF2 etching of the Si overlayer 806 for two pulses of about 100 seconds each.
a) is a microscope image 900 of a cantilever structure 902 of the sample 800 (
Similar effects are observed for another example embodiment comprising a ZnO bridge and for yet another example embodiment comprising a 500 nm ZnO layer sputtered on a 100 nm Si overlayer.
Returning to
In another example embodiment, ZnO is sputtered on bonded SOI substrates. The substrates can be 2 or 4-in.-diameter commercial grade bonded SOI structures comprising a Si (111) device layer (about 3±0.5 μm thickness), a 2.0 to 2.5 μm thick buried SiO2 layer, and a Si (111) handle substrate (about 400±25 μm thickness). The orientation of the SOI (111) layers are tilted by 0.5°±4° off axis. Using a conventional RF Magnetron system, ZnO material thickness of about 2.5 μm and about 1.0 μm respectively is sputtered directly onto the bonded SOI substrates.
a) is a schematic diagram illustrating a sample 1000 in the example embodiment. The sample 1000 comprises a Si(111) bonded SOI substrate 1002 that includes an “inherent” SiO2 layer 1004 of about 2.0 μm thickness and an “inherent” Si overlayer 1006 of about 3.0 μm thickness. The sample 1000 further comprises a ZnO layer 1008 of about 2.5 μm thickness sputtered on the Si overlayer 1006, without depositing an additional or “dedicated” sacrificial layer.
Thus, it will be appreciated that the control of airgap thickness is advantageously separated from the device buildup processes and is provided by a control of the “inherent” Si overlayer thickness.
A 77 K PL measurement is conducted using a micro-PL setup.
In the example embodiment, the ZnO layer 1008 is patterned with features of varying bridges and cantilever lengths using standard photolithography and etched for a period of about 20 mins to a depth of about 3.0 μm using constant process parameters of about 20 sccm BCl3 flow, 10 sccm Cl2 flow, 500 W ICP power, 200 W RIE power, 5 mTorr pressure and 6° C. temperature. The sample 1000 is subjected to XeF2 etching of Si layer 1006 for a single pulse of about 30 seconds.
a) is a microscope image 1100 showing a ZnO bridge structure 1102 of the sample 1000 (
a) is a SEM image 1200 of a released ZnO bridge structure 1202 of the sample 1000 (
In the example embodiment, the released ZnO micro-bridge structure 1102 (
c) is a Raman mapping diagram of E2 phonon intensity in the ZnO micro-bridge structure 1102 (
In another example embodiment, ZnO is provided on bulk Si(111) substrates. In the example embodiment, SEM images of bridge and cantilever structures before and after subjecting to XeF2 dry release/etching confirm the undercut etching. In optical microscopy images (not shown), the change in the contrast with respect to the ZnO platform and bridge indicates that the underlying Si material of the substrates has been etched.
a) is a SEM image 1400 of a released ZnO bridge structure 1402 on bulk Si(111) platforms 1404, 1406.
In yet another example embodiment, nanocrystalline and microcrystalline diamond mechanical structures are provided on silicon. The nanocrystalline diamond (NCD) microstructures are patterned by ICP etching prior to XeF2 etching. For the ICP etching, Al hard masks are used for dry etching of diamond with Ar/O2 plasma.
a) is a SEM image 1500 of freestanding NCD cantilever structures e.g. 1502 in the example embodiment. The NCD cantilever structures e.g. 1502 have been subjected to about 2 mins of XeF2 etching. A change in the contrast within the area of the cantilever structures e.g. 1502 can be observed in the microscope image 1504 shown in the inset. The change in the contrast can also be observed in the SEM image 1500.
b) is a SEM image 1506 of a freestanding NCD bridge structure 1508 in the example embodiment. The NCD bridge structure 1508 has been subjected to about 2 mins of XeF2 etching. A change in the contrast within the area of the bridge structure 1508 can be observed in the microscope image 1510 shown in the inset. The change in the contrast can also be observed in the SEM image 1506.
In the example embodiment, the diamond micromechanical structures 1502, 1508 are mechanically stable.
In another example embodiment, similar fabrication steps are employed to realize chemical vapour deposition (CVD)-grown microcrystalline diamond mechanical structures.
In another example embodiment, GaN-based light emitting diode (LED) and field effect transistor (FET) micromechanical structures are provided. To fabricate photonic and mechanical sensors, freestanding LEDs and field effect transistors are fabricated on silicon and SOI platforms.
a) is an optical microscope image 1702 showing a LED microstructure membrane 1704 on a bulk silicon platform in the example embodiment.
In the example embodiment, the underetched structures are created by the XeF2 dry release technique. Such mechanical structures are suitable for photonic sensing. Apart from using InGaN/GaN, AlGaN/GaN FET cantilevers can be fabricated on both bulk silicon and SOI platforms. The undercut etching of the mechanical structures is highly selective and the final device release is achieved by XeF2 dry etching of silicon and SOI.
In yet another example embodiment, GaN-based undercut microdisk LED structures are provided.
In the example embodiment, the vertical microdisk LED structures are processed with top p-bond pad and p-contact metallization. The representative electro-luminescence (EL) spectrum from such microdisk LED devices is shown in
In the above example embodiments, a II-VI wide bandgap semiconductor micromechanical structure or a III-V wide bandgap semiconductor micromechanical structure can be realized on SOI substrates. The SOI substrates can be prepared by wafer bonding and/or separation by implantation of oxygen (SIMOX). The SOI platforms may be of both (100) and (111) orientations. The SOI substrates of different orientations can result in a specific stress which can be tailored by precisely controlling the thickness of silicon over layers. The types of II-VI wide bandgap structures may include ZnO, Zn(Mg)O, Zn(Cd)O, ZnS related materials of single and heterostructure configurations with varying thickness. The types of III-V wide bandgap structures may include GaN, AlN, AlGaN, InGaN, and InN related materials of single and heterostructure configurations with varying thickness. The example embodiments are also applicable for polycrystalline and nanocrystalline diamond micromechanical structures on bulk Si and SOI substrates. The types of II-VI and III-V wide bandgap layers used to realize overhanging structures can provide controlled residual stress after sacrificial etching of silicon. The silicon of the substrates for dry etching are exposed via standard lithography techniques. The example embodiments can also provide wide bandgap semiconductor micromechanical structures such as an optoelectronic device comprising material such as e.g. InGaN/GaN-, AlGaN/GaN-, ZnMgO/ZnO-based light emitting diodes (LEDs) on bulk Si and SOI platforms. The example embodiments can also provide wide bandgap semiconductor micromechanical structures such as a microelectronic device comprising material such as e.g. AlGaN/GaN-, InAlN/GaN, ZnO/GaN-based hybrid field effect transistors (FETs) and high electron mobility transistors (HEMTs).
In the described example embodiments, the sacrificial release of Si and SOI is after the deposition of e.g. the wideband gap structures using various growth techniques. There is a growth-induced stress in such lattice and thermal mismatched materials grown on top of SOI and bulk Si. After device release, a bending stress component appears and is dependent on the layer thickness and geometrical dimensions. Such stress can also be significantly influenced by pre-designed growth-induced stress. Thus, by controlling these parameters, mechanical structures with predicted stress values may be designed using sacrificial dry release.
It will be appreciated by a person skilled in the art that numerous variations and/or modifications may be made to the present invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects to be illustrative and not restrictive.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/SG07/00386 | 11/9/2007 | WO | 00 | 3/30/2010 |
Number | Date | Country | |
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60858076 | Nov 2006 | US |