Patent Application
20250098249
Integrated circuit (IC) fabrication usually includes two stages. The first stage is referred to as the “front-end of line (FEOL),” and the second stage is referred to as the “back-end of line (BEOL).” In the FEOL, individual semiconductor device components (e.g., transistor, capacitors, resistors, etc.) can be formed over a support structure (e.g., a wafer, a substrate, a die, or a chip; also referred to herein as, simply, “support”), occupying one or more layers referred to as “FEOL layers.” In the BEOL, metal layers, vias, and insulating layers can be formed above the FEOL layers to get the individual components of the FEOL layers interconnected. The BEOL usually starts with forming the first metal layer on the wafer. The first metal layer is often called M0. More metal layers can be formed on top of M0, electrically insulated from one another by insulating layers except for the conductive vias that may extend through the insulating layers to enable electrical connectivity between elements of different metal layers. These metal layers are often called M1, M2, and so on, and are collectively referred to as BEOL layers.
Conventionally, power has been provided from the front side of an IC device, i.e., the face of an IC device that is above the BEOL layers so that the BEOL layers are between said front side and the one or more FEOL layers. Recently, some IC devices have been implemented with backside power delivery, i.e., with power delivery from the face of an IC device that is opposite the front side (such a face referred to as a “back side”). Such implementations are based on performing back side reveal to remove some or all of the support over which the FEOL components were formed and then providing one or more layers of interconnects such as conductive lines and conductive vias for routing power at the revealed back side.
Backside power delivery may provide advantages in terms of easier fabrication, decreased complexity of power routing, and ability to include various IC components (e.g., capacitors, inductors, resistors, etc.) for reducing the parasitic effects of IC devices, e.g., for reducing parasitic effects associated with the interconnects used for power delivery. However, it also has challenges. Backside power delivery is based on using deep trench vias that extend between the front side and the back side of the IC devices, and one challenge is undesirable shifts in threshold voltages of transistors when a deep trench via is placed in the vicinity of transistors, a phenomenon that may be referred to as a “deep trench via proximity effect.”
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
Disclosed herein are IC structures and devices that aim to mitigate (e.g., reduce or eliminate) proximity effects of deep trench vias. In some embodiments, deep trench vias may be used for backside power/signal/ground delivery. The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating mitigation of proximity effects of deep trench vias, proposed herein, it might be useful to first understand phenomena that may come into play when deep trench vias are implemented. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
For the past several decades, the scaling of features in IC structures has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize every portion of IC structures becomes increasingly significant. Careful design of deep trench vias may help with such an optimization.
Typically, metallization of deep trench vias is performed in a substantially the same time as metallization of source/drain (S/D) contacts (i.e., contacts to transistors' source and drain regions). In this context, metallization is a process of filling the openings for deep trench vias and openings for S/D contacts with electrically conductive materials such as metals or metal alloys. In order to improve electrical contact between the electrically conductive materials of S/D contacts and S/D regions, a thin layer of an interfacial material is sometimes deposited over the S/D regions, before the rest of the S/D contact openings are filled with the electrically conductive materials. Conventionally, titanium has been used as the material of choice for such interfacial material, deposited by a conformal deposition method such as physical vapor deposition (PVD) over the bottoms and sidewalls of S/D contact openings. Titanium at the bottoms of S/D contact openings may then form titanium silicide with the silicon-based material of S/D regions (e.g., doped silicon), improving electrical contact to S/D regions by reducing contact resistance. Because metallization of deep trench vias is performed at the same time, titanium is also deposited at the bottoms and sidewalls of the openings for deep trench vias.
Embodiments of the present disclosure are based on recognition that, while presence of titanium at the bottom of S/D contact openings is beneficial for reduced contact resistance, it may not be the case for titanium deposited on the sidewalls of the openings for the deep trench vias. In particular, it may be the case that presence of titanium on the sidewalls of deep trench vias contributes to the undesirable shifts in threshold voltages of transistors, described above. Embodiments of the present disclosure are further based on recognition that replacing the PVD process for deposition of titanium with selective deposition may help mitigate deep trench via proximity effect. Selective deposition refers to a set of fabrication processes that allow for the controlled and precise deposition of materials onto specific areas while avoiding deposition on other areas. Using selective deposition techniques to deposit titanium onto S/D regions may allow reducing or eliminating presence of titanium on sidewalls of S/D contacts as well as on sidewalls of deep trench vias. In turn, this may reduce or eliminate deep trench via proximity effect.
Implementing selective titanium deposition during metallization of deep trench vias and S/D contacts may result in several features characteristic of the use of such deposition in the final IC structures. For example, in one aspect, an example IC structure fabricated using selective titanium deposition may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.
While some descriptions are provided herein with respect to the use of deep trench vias for backside power delivery, embodiments of the present disclosure are equally applicable to using deep trench vias for backside signal or ground delivery, as well as to deep trench vias being used for purposes of delivering power, signal, or ground to IC components from the front side. Furthermore, while some descriptions are provided herein with respect to nanoribbon transistors, implementing selective titanium deposition for mitigation of deep trench via proximity effects is equally applicable to non-planar transistors other than nanoribbon transistors (e.g., to FinFETs), as well as to planar transistors. Still further, while descriptions are provided herein with respect to titanium being the interface material used to provide an interface between S/D regions and conductive fill material(s) of S/D contacts, these descriptions are equally applicable to selective deposition of material other than titanium, which material would be selected for a specific design.
IC structures as described herein, in particular IC structures fabricated using selective titanium deposition during S/D contact metallization, may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, IC structures as described herein may be included in a radio frequency IC (RFIC), which may, e.g., be included in any component associated with an IC of an radio frequency (RF) receiver, an RF transmitter, or an RF transceiver, e.g., as used in telecommunications within base stations (BS) or user equipment (UE). Such components may include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including arrays of RF filters, or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, IC structures as described herein may be included in memory devices or circuits. In some embodiments, IC structures as described herein may be employed as part of a chipset for executing one or more related functions in a computer.
For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value, e.g., within +/−5% of a target value, based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−10% of a target value, e.g., within +/−5% of a target value, based on the context of a particular value as described herein or as known in the art.
In the following description, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, while some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the fabricating processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC structures fabricated using selective titanium deposition during S/D contact metallization as described herein.
Various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms “oxide,” “carbide,” “nitride,” “silicide,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, silicon, etc.; the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide; the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. Materials referred to herein with formulas or as compounds cover all materials that include elements of the formula or a compound, e.g., TiSi or titanium silicide may refer to any material that includes titanium and silicon, WN or tungsten nitride may refer to any material that includes tungsten and nitrogen, etc. The term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. A first component described to be electrically coupled to a second component means that the first component is in conductive contact with the second component (i.e., that a conductive pathway is provided to route electrical signals/power between the first and second components).
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. Although some materials may be described in singular form, such materials may include a plurality of materials, e.g., a semiconductor material may include two or more different semiconductor materials.
Fabrication of IC structures using selective titanium deposition during S/D contact metallization may be carried out with transistors of any architecture, such as any non-planar or planar architecture. Non-planar transistors such as double-gate transistors, tri-gate transistors, FinFETs, and nanowire/nanoribbon/nanosheet transistors refer to transistors having a non-planar architecture. In comparison to a planar architecture where the transistor channel has only one confinement surface, a non-planar architecture is any type of architecture where the transistor channel has more than one confinement surfaces. A confinement surface refers to a particular orientation of the channel surface that is confined by the gate field. Non-planar transistors potentially improve performance relative to transistors having a planar architecture, such as single-gate transistors.
Nanoribbon transistors may be particularly advantageous for continued scaling of complementary metal-oxide-semiconductor (CMOS) technology nodes due to the potential to form gates on all four sides of a channel material (hence, such transistors are sometimes referred to as “gate all around” transistors). Therefore, some IC structures illustrated herein show nanoribbon transistors as an example (e.g., IC structures shown in
As used herein, the term “nanoribbon” refers to an elongated structure of a semiconductor material having a longitudinal axis parallel to a support structure (e.g., a substrate, a die, a chip, or a wafer) over which such a structure is built. Typically, a length of a such a structure (i.e., a dimension measured along the longitudinal axis, shown in the present drawings to be along the y-axis of an example x-y-z coordinate system 105 shown in
Implementations of the present disclosure may be formed or carried out on any suitable support 102, such as a substrate, a die, a wafer, or a chip. The support 102 may, e.g., be the wafer 1500 of
The nanoribbon 104 may take the form of a nanowire or nanoribbon, for example. In some embodiments, an area of a transversal cross-section of the nanoribbon 104 (i.e., an area in the x-z plane of an x-y-z coordinate system 105 shown in
In various embodiments, the semiconductor material of the nanoribbon 104 may be composed of semiconductor material systems including, for example, N-type or P-type materials systems. In some embodiments, the nanoribbon 104 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 104 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 104 may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 104 may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb).
For some example N-type transistor embodiments (i.e., for the embodiments where the transistor 110 is an N-type metal-oxide-semiconductor (NMOS) transistor), the channel material of the nanoribbon 104 may include a III-V material having a relatively high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material of the nanoribbon 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). For some example P-type transistor embodiments (i.e., for the embodiments where the transistor 110 is a P-type metal-oxide-semiconductor (PMOS) transistor), the channel material of the nanoribbon 104 may advantageously be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material of the nanoribbon 104 may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7.
In some embodiments, the channel material of the nanoribbon 104 may be a thin-film material, such as a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide,] or tungsten oxide. In general, if the transistor formed in the nanoribbon is a thin-film transistor (TFT), the channel material of the nanoribbon 104 may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material of the nanoribbon 104 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back-end fabrication to avoid damaging other components, e.g., front-end components such as the logic devices.
A gate stack 106 including a gate electrode material 108 and, optionally, a gate insulator material 112, may wrap entirely or almost entirely around a portion of the nanoribbon 104 as shown in
The gate electrode material 108 may include one or more gate electrode materials, where the choice of the gate electrode materials may depend on whether the transistor 110 is a PMOS transistor or an NMOS transistor. For a PMOS transistor, gate electrode materials that may be used in different portions of the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, gate electrode materials that may be used in different portions of the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of a plurality of gate electrode materials, where zero or more materials of the stack are workfunction (WF) materials and at least one material of the stack is a fill metal layer. Further materials/layers may be included next to the gate electrode material 108 for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.
In some embodiments, the gate insulator material 112 may include one or more high-k dielectrics including any of the materials discussed herein with reference to the insulator material that may surround portions of the transistor 110. In some embodiments, an annealing process may be carried out on the gate insulator material 112 during fabricate of the transistor 110 to improve the quality of the gate insulator material 112. The gate insulator material 112 may have a thickness that may, in some embodiments, be between about 0.5 nanometers and 3 nanometers, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers). In some embodiments, the gate stack 106 may be surrounded by a gate spacer, not shown in
Turning to the S/D regions 114 of the transistor 110, in some embodiments, the S/D regions may be highly doped, e.g., with dopant concentrations of about 1021 cm−3, in order to advantageously form Ohmic contacts with the respective S/D contacts (not shown in
The S/D regions 114 of the transistor 110 may generally be formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the nanoribbon 104 to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the nanoribbon 104 may follow the ion implantation process. In the latter process, portions of the nanoribbon 104 may first be etched to form recesses at the locations of the future S/D regions 114. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 114. In some implementations, the S/D regions 114 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the S/D regions 114 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 114. In some embodiments, a distance between the first and second S/D regions 114 (i.e., a dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).
The IC structure 100 shown in
As shown in
In order to further illustrate details of the IC structure 200,
As shown in
Above the nanoribbon stack 204-1,
The S/D contacts 214 may be electrically isolated from the gate electrode material 108 and the electrically conductive material 306 of the gate contact 206 by gate spacers 308. The gate spacers 308 may include one or more of spacer materials, diffusion barrier materials, adhesion materials, etc., as known in the art for forming contacts to various components of IC structures. In some embodiments, the gate spacers 308 may include low-k dielectrics and/or any of the ILD materials described above. Optionally, sidewalls of the S/D contacts 214 may be lined with one or more liners 310, where the liners 310 may include, but not limited to, materials comprising silicon and nitrogen (e.g., silicon nitride), materials comprising silicon and oxygen (e.g., silicon oxide), materials comprising silicon and carbon (e.g., silicon carbide), and/or their composites. Within the sidewalls, the S/D contacts 214 may be filled with an electrically conductive fill material 314. In various embodiments, material compositions of the electrically conductive fill material 314 and the electrically conductive material 306 may be substantially the same (e.g., both may include/be tungsten) or different. At the bottom of the S/D contacts 214, an interface material 316 is deposited to provide an interface between the S/D regions 114 and the electrically conductive fill material 314 of S/D contacts 214. The interface material 316 may include/be a metal such as titanium which, once deposited, may intermix with the material of the S/D regions 114, e.g., with silicon, forming a compound (e.g., titanium silicide) that may help reduce contact resistance of the S/D contacts 214. During fabrication, the interface material 316 may be deposited within openings for future S/D contacts 214 using selective deposition, where the interface material 316 is deposited onto the bottom of the openings for the S/D contacts 214 but not on the sidewalls of the openings for the S/D contacts 214. This is shown in
Because metallization of S/D contacts 214 may be performed substantially simultaneously with metallization of deep trench vias, selective deposition may result in the interface material 316 also being selectively deposited on the bottom but not on the sidewalls of deep trench vias. This is illustrated in
In some embodiments, sidewalls of the deep trench via 226 may be lined a liner 324. The liner 324 may include, but is not limited to, composite materials comprising an electrically conductive material such as tungsten and a material such as carbon or nitrogen (e.g., WCN). In some embodiments, the liner 324 may include a metal such as tantalum. However, as shown in
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors) of the device region 404 through one or more interconnect layers disposed on the device region 404 (illustrated in
In some embodiments, the interconnect structures 428 may include conductive lines 428a and/or conductive vias 428b filled with an electrically conductive material such as a metal. The lines 428a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the support 102 upon which the device region 404 is formed. For example, the lines 428a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 406 and 408 may include a dielectric material 426 disposed between the interconnect structures 428, as shown in
A first interconnect layer 406 may be formed above the device region 404. In some embodiments, the first interconnect layer 406 may include lines 428a and/or vias 428b, as shown. The lines 428a and/or the vias 428b of the first interconnect layer 406 may be coupled with contacts (e.g., gate contacts 206 and/or S/D contacts 214 of the IC structure 200) of the device region 204.
A second interconnect layer 408 may be formed above the first interconnect layer 406. In some embodiments, the second interconnect layer 408 may include vias 428b to couple the lines 428a of the second interconnect layer 408 with the lines 428a of the first interconnect layer 406. Although the lines 428a and the vias 428b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 408) for the sake of clarity, the lines 428a and the vias 428b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
Additional interconnect layers, as desired, may be formed in succession on the second interconnect layer 408 according to similar techniques and configurations described in connection with the second interconnect layer 408 or the first interconnect layer 406. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 419 in the IC device 400A (i.e., farther away from the device region 404) may be thicker. Although not specifically shown in
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors) of the device region 404 through one or more interconnect layers disposed on the back side of the device region 404 (illustrated in
In some embodiments, the interconnect structures 458 may include conductive lines 458a and/or conductive vias 458b filled with an electrically conductive material such as a metal. The interconnect layers 436 and 438 may include a dielectric material 456 disposed between the interconnect structures 458, as shown in
IC devices/structures fabricated using selective titanium deposition during S/D contact metallization as described herein (e.g., as described with reference to
The IC devices disclosed herein, e.g., the IC devices 100, 200, or 400, or any variations thereof, may be included in any suitable electronic component.
The package substrate 1652 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed of different materials, etc.), and may have conductive pathways extending through the dielectric material between the face 1672 and the face 1674, or between different locations on the face 1672, and/or between different locations on the face 1674. These conductive pathways may take the form of any of the interconnects 428 discussed above with reference to
The package substrate 1652 may include conductive contacts 1663 that are coupled to conductive pathways (not shown) through the package substrate 1652, allowing circuitry within the dies 1656 and/or the interposer 1657 to electrically couple to various ones of the conductive contacts 1664 (or to devices included in the package substrate 1652, not shown).
The IC package 1650 may include an interposer 1657 coupled to the package substrate 1652 via conductive contacts 1661 of the interposer 1657, first-level interconnects 1665, and the conductive contacts 1663 of the package substrate 1652. The first-level interconnects 1665 illustrated in
The IC package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of the dies 1656, first-level interconnects 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to conductive pathways (not shown) through the interposer 1657, allowing circuitry within the dies 1656 to electrically couple to various ones of the conductive contacts 1661 (or to other devices included in the interposer 1657, not shown). The first-level interconnects 1658 illustrated in
In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first-level interconnects 1665, and a mold compound 1668 may be disposed around the dies 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. Example materials that may be used for the underfill material 1666 and the mold compound 1668 are epoxy mold materials, as suitable. Second-level interconnects 1670 may be coupled to the conductive contacts 1664. The second-level interconnects 1670 illustrated in
The dies 1656 may take the form of any of the embodiments of the die 1502 discussed herein. In embodiments in which the IC package 1650 includes multiple dies 1656, the IC package 1650 may be referred to as a multi-chip package (MCP). The dies 1656 may include circuitry to perform any desired functionality. For example, or more of the dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of the dies 1656 may be memory dies (e.g., high-bandwidth memory).
Although the IC package 1650 illustrated in
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the package interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to through-silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic RAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).
In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC structure, including a transistor including a region of a doped semiconductor material, where the region is either a source region or a drain region of the transistor; and a contact structure coupled to the region, the contact structure including an interface material and a fill material, where, within the contact structure, the interface material is limited to an area between (e.g., directly between) the region and the fill material.
Example 2 provides the IC structure according to example 1, where the interface material is limited to the area between the region and the fill material by being at a bottom of the contact structure and being substantially absent from sidewalls of the contact structure.
Example 3 provides the IC structure according to examples 1 or 2, further including a device region, where: the transistor and the contact structure to the region are within the device region, the device region has a first face and a second face, the second face being opposite the first face, the device region further includes a conductive via extending between the first face and the second face, and the interface material is absent from sidewalls of the conductive via or a concentration of the interface material at the sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.
Example 4 provides the IC structure according to example 3, where the conductive via includes an electrically conductive fill material and where sidewalls of the conductive via are surrounded by an insulator material.
Example 5 provides the IC structure according to example 4, where, at the sidewalls of the conductive via, the electrically conductive fill material is in contact with the insulator material.
Example 6 provides the IC structure according to example 4, where the conductive via further includes a liner material, and where, at the sidewalls of the conductive via, the electrically conductive fill material is in contact with the liner material, and the liner material is in contact with the insulator material.
Example 7 provides the IC structure according to example 6, where the liner material includes carbon or nitrogen.
Example 8 provides the IC structure according to examples 6 or 7, where the liner material either excludes the interface material or a concentration of the interface material within the liner material is below about 1015 atoms per cubic centimeter.
Example 9 provides the IC structure according to any one of examples 4-8, where the electrically conductive fill material includes tungsten.
Example 10 provides the IC structure according to any one of the preceding examples, where the interface material is titanium.
Example 11 provides the IC structure according to any one of the preceding examples, where the doped semiconductor material includes silicon, and the interface material includes titanium and silicon (e.g., titanium silicide).
Example 12 provides the IC structure according to any one of the preceding examples, where a thickness of the interface material in the area between the region and the fill material is below about 5 nanometers.
Example 13 provides the IC structure according to any one of the preceding examples, where, within the contact structure, one side of the interface material is in contact (e.g., in direct contact) with the fill material and another side of the interface material is in contact (e.g., in direct contact) with the doped semiconductor material.
Example 14 provides an IC structure, including a device region having a first face and a second face, the second face being opposite the first face; and a conductive via extending between the first face and the second face, where the conductive via includes an electrically conductive material, and where a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.
Example 15 provides the IC structure according to example 14, where the device region includes a transistor, and a contact coupled to a source region of the transistor, where a portion of the contact closest to the source region includes an interface material, and the interface material includes titanium.
Example 16 provides the IC structure according to example 15, where titanium is substantially absent from sidewalls of the contact.
Example 17 provides the IC structure according to any one of examples 14-16, further including a plurality of first interconnects at the first face of the device region, and a plurality of second interconnects at the second face of the device region, where: the conductive via is electrically connected to at least one of the first interconnects or at least one of the second interconnects, in a cross-section substantially perpendicular to the device region, each of the conductive via, the at least one of the first interconnects, and the at least one of the second interconnects has a trapezoidal shape having a first side and a second side, where the first side is substantially parallel to the second side and shorter than the second side, for the trapezoidal shape of the at least one of the first interconnects and the trapezoidal shape of the conductive via, the first side is closer to the second interconnects than the second side, and for the trapezoidal shape of the at least one of the second interconnects, the first side is closer to the device region than the second side.
Example 18 provides a method of fabricating an IC structure, the method including providing a channel material over a portion of a support; forming a source region of a transistor in the channel material; providing a further material over the source region; forming an opening extending through the further material to expose a portion of the source region; performing selective deposition to deposit titanium at a bottom of the opening without substantially depositing titanium on sidewalls of the opening; and after performing selective deposition, filling the opening with an electrically conductive material.
Example 19 provides the method according to example 18, where the portion of the support is a first portion, the opening is a first opening, the electrically conductive material is a first electrically conductive material, and the method further includes providing an insulator material over a second portion of the support; forming a second opening extending into the insulator material; performing selective deposition to deposit titanium at a bottom of the second opening without substantially depositing titanium on sidewalls of the second opening; and after performing selective deposition to deposit titanium at the bottom of the second opening, filling the second opening with a second electrically conductive material.
Example 20 provides the method according to example 19, where selective deposition to deposit titanium at the bottom of the first opening is performed substantially simultaneously with performing selective deposition to deposit titanium at the bottom of the second opening.
Example 21 provides the method according to any one of examples 18-20, where the IC structure is an IC structure according to any one of the preceding examples.
Example 22 provides an IC package that includes an IC die including an IC structure according to any one of examples 1-17; and a further IC component, coupled to the IC die.
Example 23 provides the IC package according to example 22, where the further IC component includes a package substrate.
Example 24 provides the IC package according to example 22, where the further IC component includes an interposer.
Example 25 provides the IC package according to example 22, where the further IC component includes a further IC die.
Example 26 provides a computing device that includes a carrier substrate and an IC structure coupled to the carrier substrate, where the IC structure is an IC structure according to any one of examples 1-17, or the IC structure is included in the IC package according to any one of examples 22-25.
Example 27 provides the computing device according to example 26, where the computing device is a wearable or handheld computing device.
Example 28 provides the computing device according to examples 26 or 27, where the computing device further includes one or more communication chips.
Example 29 provides the computing device according to any one of examples 26-28, where the computing device further includes an antenna.
Example 30 provides the computing device according to any one of examples 26-29, where the carrier substrate is a motherboard.
Example 31 provides the IC structure according to any one of examples 1-17, where the IC structure includes or is a part of a central processing unit.
Example 32 provides the IC structure according to any one of examples 1-31, where the IC structure includes or is a part of a memory device, e.g., a high-bandwidth memory device.
Example 33 provides the IC structure according to any one of examples 1-32, where the IC structure includes or is a part of a logic circuit.
Example 34 provides the IC structure according to any one of examples 1-33, where the IC structure includes or is a part of input/output circuitry.
Example 35 provides the IC structure according to any one of examples 1-34, where the IC structure includes or is a part of an FPGA transceiver.
Example 36 provides the IC structure according to any one of examples 1-35, where the IC structure includes or is a part of an FPGA logic.
Example 37 provides the IC structure according to any one of examples 1-36, where the IC structure includes or is a part of a power delivery circuitry.
Example 38 provides the IC structure according to any one of examples 1-37, where the IC structure includes or is a part of a III-V amplifier.
Example 39 provides the IC structure according to any one of examples 1-38, where the IC structure includes or is a part of PCIE circuitry or DDR transfer circuitry.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
