The present invention relates to the preparation of layout data for use in a photolithographic processing system and, in particular, to resolution enhancement techniques for improving the quality of a printed layout pattern on a semiconductor wafer.
In conventional photolithographic processing, integrated circuits are created on a semiconductor wafer by exposing the wafer with a pattern of features on a mask or reticle. The pattern of features selectively exposes photosensitive chemicals on a wafer that is then further chemically and mechanically processed to build up layers of the integrated circuit.
As the features on a mask become smaller and smaller, optical distortions can occur whereby the exposure pattern created on a wafer will not match the pattern of features on the mask. To correct this, numerous resolution enhancement techniques (RETs) may be employed to improve the image quality so that the exposure pattern on a wafer more faithfully matches the pattern of features desired. Such RETs often comprise making extensive changes to the corresponding pattern of features on a mask to compensate for the known distortions in the imaging process.
With conventional resolution enhancement techniques, data for a pattern of mask features are analyzed with a computer program to estimate how a corresponding pattern of features will print on a mask. The data for the individual mask features or portions thereof may be adjusted such that the pattern created on the wafer will more faithfully match the desired layout. In addition, features, such as subresolution assist features (SRAFs), may be added to the layout data as necessary to improve printing fidelity. Typically, SRAFs are rectangular elements that are positioned adjacent to an edge of a feature in order to improve the contrast of the feature. The shape, size and placement of the SRAFs are typically predetermined, and often follow simple geometric rules.
While conventional resolution enhancement techniques are functional at compensating for some process distortions, a better match between the image produced and the image desired can be achieved.
To further improve the fidelity of a lithographic image to the desired layout pattern, the present invention is a system for generating mask layout data that approximates an optimized mask layout pattern that has been calculated to print a target pattern of features with a photolithographic process. The target layout pattern or portion thereof is received and the optimized mask layout pattern is calculated using the target layout pattern and the known parameters of a photolithographic printing system. The optimized mask layout pattern includes a number of printing features that correspond to features in the target layout and a number of non-printing features. In one embodiment of the invention, the mask layout data is generated from the optimized mask layout pattern by approximating one or more of the non-printing features as sub-resolution assist features (SRAFs). These SRAFs can in particular be generated with further constraints and criteria based on manufacturability parameters derived from the mask fabrication and/or wafer manufacturing processes.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
As indicated above, the present invention is a system for approximating an optimized mask layout pattern for use in printing a target pattern of features with a photolithographic process.
In the example shown, the target features 8a-8h, etc. are square or rectangular contact pads in an integrated circuit. In the example, the normal 4× magnification of the mask features over the wafer features has also been assumed, and mask features are shown at the same scale of the corresponding wafer.
In one embodiment of the invention, the optimized mask layout pattern shown in
From the target layout data received and the known properties of the photolithographic system that will be used to print the mask layout data on a wafer, a calculation is performed with a computer system to determine what the optimized mask layout pattern should be in order to actually print the target layout of features 8 on a wafer. In one embodiment of the invention, the calculation of the optimized mask layout pattern comprises creating an inverse image of the target pattern using Fourier transforms and numerical de-convolution. In one embodiment of the invention, a gradient of an objective function based on the difference between a simulated image of the mask layout and the target image is generated analytically by convolution, and individual pixels in the mask layout are systematically changed to minimize this objective function. In one embodiment of the invention, the changes to the individual pixels can be further constrained by additional mask constraints, such as a minimum pixel size, total number of mask writer shots, or other mask writing limitations. In one embodiment of the invention, the calculation of the optimized mask layout pattern comprises optimizing both the mask and the illumination.
In one embodiment of the invention, the calculation of the optimized mask layout pattern is performed in accordance with techniques described in the paper “Solving Inverse Problems of Optical Microlithography” by Yuri Granik, published in Optical Microlithography XVIII, Proceedings of the SPIE Vol. 5754, pp. 506-526 (May 2005) and contained in U.S. Provisional Application No. 60/658,278, which are expressly incorporated by reference. In another embodiment of the invention, the optimized mask layout pattern is calculated in the manner described in U.S. Provisional Patent Application No. 60/722,840, titled “Fast Pixel-Based Mask Optimization for Inverse Lithography” by Yuri Granik, which is filed concurrently herewith and expressly incorporated by reference herein.
As used herein, the term “optimized” mask layout pattern refers to a layout pattern that is calculated mathematically from the target layout data and one or more optical parameters, e.g., illumination system, numerical aperture NA, illumination wavelength λ, etc. and process parameters such as print bias, resist threshold, etch bias, etc.
Once the optimized mask layout pattern has been calculated for printing the target pattern of features on a wafer, the non-printing features of the mask pattern are analyzed. Some of the non-printing features, for example, feature 12a, completely surround a printing feature, i.e., feature 10a. Other non-printing features, e.g., feature 12e, are merely nearby a corresponding printing feature, e.g., 10g. As indicated above, the optimized mask layout pattern also includes a number of second order non-printing features 14a, 14b, etc. For example, feature 14a is a second order feature to the printing feature 10a because it is farther away from the printing feature 10a than the primary or first order non-printing feature 12a.
As can be seen, the non-printing features shown in
One method of generating mask features that approximate one or more of the non-printing features in the optimized mask layout pattern is shown in
If the analysis window 52 is not square, the orientation of the window can be changed and the window stepped through the search area 50 again. In the example shown, the analysis window 52 is rotated by 90 degrees to be two grid cells wide and four grid cells high to capture vertically oriented portions of the non-printing features.
In some instances, a mask writer can write geometries at an angle such as ±45 degrees. Therefore, if the mask layout data is to be used with such a mask writer, the optimized mask layout pattern can be rotated by ±45 degrees and the above process of searching areas with an analysis window repeated.
As will be appreciated, each of the polygons 60-74 is initially defined as a series of rectangular (or other shape) polygons corresponding to the shape of the analysis window. For example, a single polygon may be defined for each group overlapping polygons by including the outer perimeter of the overlapping polygons. The combined polygon defines a subresolution assist feature within the mask layout data because the polygon is not large enough to print on a wafer but does aid in printing a target feature.
Once the mask data are determined that approximate one or more of the non-printing features of optimized mask layout pattern, a data clean-up step can be executed. In one embodiment, polygons or portions thereof in the mask layout data that overlap can be removed if the density of one of the overlapping polygons is less than that of another. Similarly, the maximum width of an individual polygon can be thinned to have a width that is less than the maximum width of a non-printing feature for the photolithographic processing system to be used. Similarly, the maximum length of any polygon can be shortened to be less than the length of a maximum non-printing feature.
In yet another embodiment, irregularly shaped polygons that approximate a non-printing feature or portion thereof can be simplified to remove jogs or other features that are difficult to write on a mask, or the shot count has increased to such a degree that the write time is too long. The exact parameters and limitations of the clean-up step can be selected by a user, and can use criteria based on rules derived from the printing capabilities of the mask writer or can be based on a model simulation of how the polygons will behave during photolithographic processing.
Although the embodiment of the present invention described operates to create mask layout data features that approximate one or more first order, non-printing features in the optimized mask layout pattern, it will be appreciated that polygons that approximate the second order or higher non-printing features could also be included in the mask layout data if desired.
At 104, the non-printing features of the optimized mask layout pattern are identified. These can be copied to a separate data layer containing only these non-printing features, or remain in a data layer merged with printing features. At 106, mask features are defined that approximate all or a portion of one or more of the non-printing features. As described above, in one embodiment of the invention, subresolution assist features are defined to approximate only the first order non-printing features. However, subresolution assist features that approximate higher order non-printing features can be included in the mask layout data, if desired. At 108, the mask layout data is created by merging the printing features and the sub-resolution assist features corresponding to the non-printing features and is stored in a database.
The data for the printing features can be either the polygons 10 computed in the optimized mask layout pattern or can be the polygons that describe the original target features 8. The mask layout data, including the data for the target features and the data that correspond to the non-printing features, is then finalized. In some embodiments of the invention, additional analysis and correction of the mask layout data may be performed (such as DRC, OPC, PSM, etc.) at 110. At 112, the finalized data is converted to standard encapsulation formats such as GDS-II or OASIS, or converted (fractured) into mask writer formats (MEBES, Hitachi, .MIC, etc.). At 114, the finalized, converted mask data is exported, for example, to a mask writer to create one or more masks used for creating the target pattern features on a semiconductor wafer.
The computer system 200 may be a stand alone, single or multiprocessor device or may be a networked or parallel processing computer system. In addition, the computer system 200 may be connected by a communication link 220, such as the Internet, to one or more remotely located computers 240. Target layout data can be retrieved from the layout database and transmitted to the remotely located computer 240, which may be inside or outside the United States, to perform the mask data calculations as described above. Mask layout data from the remotely located computer 240 can be returned to the computer system 200 or transmitted directly to the mask writer 210 to create one or more corresponding masks or reticles.
While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the scope of the invention. It is therefore intended that the scope of the invention be determined from the following claims and equivalents thereof.
The present application claims the benefit of U.S. Provisional Application No. 60/658,278, filed Mar. 2, 2005.
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