Patent Application
20240086607
Submicron manufacturing uses lithographic techniques to build up layers of materials on a substrate to create transistors, diodes, light-emitting diodes (LEDS), capacitors, resistors, inductors, sensors, wires, optical wires, microelectromechanical systems (MEMS) and other elements which collectively produce a device that serves some function. Substrate lithography is a printing process in which a mask, sometimes called a reticle, is used to transfer patterns to a substrate to create the device. In the production or manufacturing of a device, such as an integrated circuit or a flat panel display, substrate lithography may be used to fabricate the device. When the device to be created is an integrated circuit, typically the substrate is a silicon wafer. In creating an integrated circuit, the lithography is semiconductor lithography which for high volume production is typically a substrate lithography. Other substrates could include flat panel displays, liquid panel display, a mask for flat panel display, nanoimprint masters, or other substrates, even other masks.
In semiconductor lithography, the mask or multiple masks may contain a circuit pattern corresponding to an individual layer, or a part of a layer in multiple patterning processes, of the integrated circuit. This pattern can be imaged onto a certain area on the substrate that has been coated with a layer of radiation-sensitive material known as photoresist or resist. Once the patterned layer is transferred the layer may undergo various other processes such as etching, ion-implantation (doping), metallization, oxidation, and polishing. These processes are employed to finish an individual layer in the substrate. If several layers are required, then the whole process or variations thereof will be repeated for each new layer. Eventually, a combination of multiples of devices, which may be integrated circuits, will be present on the substrate. These devices may then be separated from one another by dicing or sawing and then may be mounted into individual packages.
Optical lithography may be 193 nm light, with or without immersion, or extreme ultraviolet (EUV) or X-ray lithography, or any other frequencies of light or any combination thereof.
Optical lithography that uses 193 nm light waves works with refractive optics and transmissive photomasks or reticles. The masks block, partially block, or transmit the light waves selectively on to a substrate, which is typically resist-coated during the lithographic process, to partially expose or to expose different parts of the substrate or some material on the substrate. The masks are typically at 4× magnification of the target substrate dimensions.
Extreme Ultraviolet Lithography (EUV) uses approximately 13.5 nm wavelength of light with reflective optics. Some implementations use an anamorphic mask with magnifications of 8× in one dimension and 4× in the other dimension.
In general, smaller wavelengths of light are able to resolve finer geometries, finer spaces in between geometries, and a higher frequency (density) of features on the substrate. Also in general, smaller wavelengths of light are more difficult to reliably produce and control. Economically, it is best to use the largest wavelength of light that is able to resolve the feature sizes, spaces, and frequencies that are needed for the device. It is therefore of interest to enhance the resolution achievable on the substrate with any given wavelength(s) of light.
For any lithography of a particular resolution, additional techniques such as off-axis illumination, phase shift masks, and multiple patterning extend the resolution capabilities. When multiple patterning is used, a single substrate layer is exposed multiple times, each time using a different mask which is called a mask layer.
Masks are created by electron beam (eBeam) machines, which shoot electrons at a photo resist coating a surface, which is then processed to produce the desired openings in the mask. The amount of energy delivered to a spot on the mask is called the dose, which may have no energy at a dose set to 0.0 and a nominal dose set to 1.0 by convention. A pattern will be registered when the dose exceeds a certain threshold, which is often near 0.5 by convention. Critical dimension (CD) variation is, among other things, inversely related to the slope of the dosage curve at the resist threshold, which is called edge slope or dose margin.
There are a number of technologies used by eBeam machines. Three common types of charged particle beam lithography are variable shaped beam (VSB), character projection (CP), and multi-beam projection (MBP). The most commonly-used system for leading edge mask production is VSB. VSB and CP are sub-categories of shaped beam charged particle beam lithography, in which an electron beam is shaped by a series of apertures and steered to expose a resist-coated surface. MBP uses plurality of charged particle beams whereas VSB and CP machines typically have a single beam.
It is difficult to print features whose size is similar to or smaller than the wavelength of the light used for lithography. The industry has applied various techniques to address the difficulty of reliably printing a desired shape on the substrate. A computational lithography field has emerged to use computing to enhance the substrate lithography, which in semiconductor lithography is also referred to as wafer lithography. Reticle Enhancement Technologies (RET) include computational methods and systems to design the target reticle shapes with which to project the desired pattern on the substrate more precisely and more reliably across manufacturing variation. RET often use computation to enhance an image on a mask, to print a desired substrate pattern more accurately and more reliably with resilience to manufacturing variation. The two common techniques in RET are Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT). OPC and ILT are often iterative optimization algorithms that adjust parameters defining the mask until the predicted pattern on wafer is within acceptable tolerances for a set or a range of conditions. OPC manipulates mask geometries and simulates the wafer pattern near target edges. ILT manipulates the mask transmission as pixels, and ILT typically simulates the entire wafer pattern, a process known as dense simulation. An iterative optimization algorithm typically consists of: (1) evaluate a proposed solution to assign a cost which is trying to be minimized; (2) if cost is below a cost criteria, stop; (3) calculate a gradient for each element of the proposed solution which would lead to a lower cost; (4) adjust the proposed solution according to the calculated gradients; (5) go back to (1). Costs are typically defined with positive values where zero is the best possible score as assumed here. However, alternative cost definitions may be used.
RET in general means to improve the printability of all desired features at nominal (expected) manufacturing conditions and within expected manufacturing variation around the nominal manufacturing conditions. Since manufacturing processes are not perfect, the design needs to be resilient to certain expected manufacturing variation. A larger process window means more resiliency to manufacturing variation, specifically that pattern discrepancies through defocus and dose variation are within an acceptable tolerance. Providing sufficient process window for as many of the features as possible is a goal of RET. The percentage of chips that function as specified after fabrication is often referred to as the yield. Many factors affect yield. Improving the process window is generally considered among those skilled in the art to correlate to improving yield.
In some embodiments, a method for reticle enhancement technology (RET) includes inputting a target wafer pattern, the target wafer pattern spanning an entire design area; dividing the entire design area into a plurality of tiles, each tile having a halo region surrounding the tile; and calculating an optimized mask, wherein the optimized mask is generated by a first trained neural network using the target wafer pattern. The calculating is performed for each tile in the plurality of tiles including its halo region.
In some embodiments, a system for reticle enhancement technology (RET) includes a computer cluster configured to receive a target wafer pattern, the target wafer pattern spanning an entire design area; and calculate an optimized mask, wherein the optimized proposed mask is generated by a trained neural network using the target wafer pattern.
In this disclosure, use of the term wafer lithography shall refer to substrate lithography in general. That is, embodiments shall be described in terms of semiconductor lithography as an example to simplify comprehension, but the embodiments apply also to other types of substrate lithography and to overall reticle enhancement technology. The term “substrate” in this disclosure can refer to a mask used in lithography, a silicon wafer, flat panel displays, a liquid panel display, a mask for flat panel display, nanoimprint masters, or other substrates, or other masks.
Conventional Techniques
Traditional semiconductor manufacturing flow 100 is depicted in
In each of the steps in
In wafer lithography, features that are needed on the substrate, referred to as main features, are found to print with greater fidelity and improved process window if extra features are added to the mask that are too small to print themselves, but nevertheless favorably affect the way nearby main features print. These extra features are called sub-resolution assist features (SRAFs). They are isolated shapes, unattached to a main feature, which are small enough not to print on the substrate.
Computing SRAFs and main feature modifications is highly compute-intensive with fragile results. Spurious extra patterns may print, the target pattern may not be fitted well, and the process window may be needlessly limited. A typical RET method has OPC verification to identify and correct hot spots. A hot spot is an area requiring ideal conditions to print properly and therefore is not resilient to manufacturing variation, or in some cases would not print properly even in ideal conditions. Hot spots lead to poor yield.
ILT often generates unexpected—i.e., non-intuitive—mask patterns which provide excellent results. ILT algorithms naturally create curvilinear shapes including many SRAFs. Curvilinear shapes have proven to be impractical for variable shaped beam (VSB) mask writing machines with conventional fracturing because very many VSB shots are required to expose the curvilinear shapes. Mask write times are a critical business factor, and VSB writing time scales with the number of VSB shots that need to be printed. When converting the mask patterns generated by inverse lithography technology (ILT) algorithms to VSB, considerable runtime is spent to convert the curvilinear shapes into an approximation that is more suitable for VSB writing, a process often referred to as Manhattanization. Model-based mask data preparation using overlapping shots can significantly reduce the write time impact. But still, curvilinear shapes take longer to write than Manhattan shapes. The recently introduced multi-beam electron beam mask writing systems write curvilinear shapes directly on a mask without taking any additional time. This enables ILT to output curvilinear shapes without the need for Manhattanization. Another significant problem with ILT is the huge computational demands of dense simulations of full mask layers of full designs, particularly full-reticle sized designs, which for semiconductor manufacturing is typically around 3.0 cm×2.5 cm in wafer dimensions.
Multi-beam writing eliminates the need to Manhattanize curvilinear shapes for VSB writing. But mask printability and resilience to manufacturing variation are still important considerations for mask shapes output by ILT. For example, shapes that are too small or too close to each other or have too sharp a turn in the contours of the shapes make it too difficult to make the masks reliably, especially across manufacturing variation.
The energy delivered by the electrons from an eBeam machine is often approximated as a point-spread function (PSF). While there are many effects that affect how the energy is spread, in eBeam-based mask making, either for variable shaped beam or for multi-beam writing, a monotonic continuous PSF is a reasonable representation of the energy distribution. In this disclosure, for ease of comprehension, a simple single Gaussian distribution will be used as the PSF, but the embodiments apply to any suitable PSF.
When the energy is delivered across a big enough area at unit dose in a Gaussian distribution, there is ample dose for the interior of the area to reach unit dose. But if the area is small, the highest dose in the interior of the area does not reach unit dose. Similarly, if the spacing between areas is large enough, the lowest dose reaches zero. But if the spacing is small, the lowest dose does not reach zero. When either the area or the spacing between the areas is small, the dose profile is shallow. Mask manufacturing processes are designed to provide ample dose margin for a reasonable area and spacing, say 100 nm lines separated by 100 nm spaces with unit dose for a typical leading edge mask for 193i lithography. Smaller areas and spacings have lower dose margin at the contour edges of the areas. The smaller the area, the worse the dose margin, if the dose applied is unit dose.
Dose margin also becomes worse for a typical mask writing process because of proximity effect correction (PEC). Mask writing with eBeam, whether VSB, CP, or MBP, has a backscatter effect that is well known in the art. Electrons hit the resist surface, and secondary electrons released by the electrons bounce around to expose the resist in a 10 micrometer scale area around the exposed location. This has the effect of scattering, a long-range effect, and thereby partially exposing the resist in the surrounding 10 micrometer scale area. The aggregate of these partial exposures from all exposures surrounding a given area is significant enough to require correction. Software-based correction for backscatter and other long-range effects is called PEC and is typically applied in-line with the mask writer at the time of mask writing. PEC in essence decreases the unit dose of a shot (or a pixel in the case of MBP) to compensate for the aggregate pre-dosing from the surrounding shots (or pixels). Nearly all production masks are written with PEC turned on in the machine. When the dose density of a 10 micrometer scale area is high, the amount of PEC applied is also high. This has the effect of reducing the height of the Gaussian (or PSF) of the exposure, and therefore reduces dose margin at the contour edges in that dense area. Therefore, a small shape written in an area of high dose density has worse dose margin than the same sized shape written in an area of low dose density.
Dose margin matters because a shallow slope means that a given percent dose change results in a larger difference in CD. Since dose margin is known by those skilled in the art to be a good proxy for a large variety, if not a majority, of sources of manufacturing variation, measuring CD variation against dose variation is an important measure of resilience to manufacturing variation.
Mask Process Correction, which may be performed offline, pipelined, or in-line with the mask writer, may manipulate shapes or doses applied to the mask in order to correct for linearity and enhance critical dimension uniformity (CDU) and line-edge roughness (LER) among other measures of resilience to manufacturing variation. Improving CDU and LER include enhancement of dose margin, and improving the uniformity of dose margin across features in the mask. Enhancement of dose margin (edge slope) is disclosed in U.S. Pat. No. 8,473,875, “Method and System for Forming High Accuracy Patterns Using Charged Particle Beam Lithography”, which is owned by the assignee of the present application. For masks to be written with VSB or CP writers, reduction in CD split also improves CDU. A CD split is when more than one shot is used to define the opposing edges of a critical dimension feature. An example of CD split is disclosed in U.S. Pat. No. 8,745,549, “Method and System for Forming High Precision Patterns Using Charged Particle Beam Lithography”, which is owned by the assignee of the present application.
In a typical semiconductor manufacturing process, RET of step 130 in
Semiconductor manufacturing and submicron manufacturing in general has followed Moore's Law, which predicts that the manufacturing infrastructure advances together to allow the resolution to improve at a relatively predictable and steady rate over time. An important aspect of Moore's Law is that computational capabilities of the infrastructure scale along with Moore's Law because effects relative to power consumption and cost—such as computing bandwidth, computing speed, memory capacity, memory access speeds, communication bandwidth, communication speed, long-term storage (whether solid-state or hard-disk) capacity and speed—also scale on Moore's Law. Introduction of new manufacturing technologies such as EUV lithography or MBP-based mask writing create a discontinuity in the computing requirements. Introduction of new computational technologies such as graphical processing unit (GPU) acceleration also create discontinuity in the computing capabilities and scalability.
Computational algorithms generally scale super-linearly with complexity of the design. This means that computing a tile with 1000 elements will generally take more than twice the computing needed for a tile with 500 elements. Depending on how much longer it takes to compute a tile with 1000 elements, it may be faster to divide it into two 500 element tiles and then stitch them back together to form the 1000 element tile. However, dividing and stitching may have complications depending on the computational task and the interaction between the tiles. There is a complex tradeoff that determines the right tile size for most efficient computing. This effect is exacerbated when the amount of memory required to store sufficient information for the design far exceeds the amount of memory available on an economically feasible computing system. In data processing for chip design or chip manufacturing, or generally any device design or device manufacturing of submicron devices, full chip designs, or more generally full-scale devices, need to be divided into much smaller tiles for most computational tasks. This is because both the amount of data that needs computing and the capacity of computing scales along with Moore's Law. The results are then stitched back together both for processing by the next step and also for error and data reporting. This is called tile-based computing. The tiles are typically rectangular but may be hexagonal or a mix of different shapes and/or sizes. Calculating the wafer pattern in a tile requires inclusion of the data surrounding the tile. The surrounding data is called a halo. The halo must be large enough to capture significant effects on the predicted pattern of the tile.
Some embodiments of this disclosure produce a Continuous Tone Mask (CTM) for large sections of the mask including an entire mask layer at once. The CTM captures the values of a continuously varying amplitude transmission coefficient map, from which transmitted intensity can be calculated. For masks for 193i projection of semiconductor wafers, systems and methods known in the art on today's computing platforms do not allow producing a CTM for larger than 400-1000 square micrometer areas in wafer dimensions at once. CTM for tiles are produced, each tile with its halos independently going through an optimization loop, then stitched together to form the entire mask layer, requiring additional processing to handle stitching artifacts. In contrast, some embodiments of the present disclosure enable an entire mask layer of 7.5 square-centimeter areas in wafer dimensions to be produced together in one large optimization loop. This disclosure describes methods and systems that avoid stitching problems in a correct-by-construction fashion by iteratively optimizing entire large sections instead of iteratively optimizing tiles of large sections independently as is known in the art. A large section may be, for example, 5 microns by 5 microns. In embodiments where the large section is the entire mask, the entire mask avoids stitching problems.
Some embodiments of this disclosure also produce a corresponding Quantized Tone Mask (QTM) for tiles of the entire design, such that the tiles can be combined to form an entire mask layer. The CTM captures the values of a continuously varying amplitude transmission coefficient map, from which transmitted intensity can be calculated. In some embodiments, a CTM is converted into a QTM, which is a 2-tone mask that allows short, smooth transitions between values on a grid and effectively locates edges between grid points. The final QTM has regularized values and feature sizes. Regularization is a procedure and formulation that can bring a CTM to a QTM with the methods described in U.S. Pat. No. 7,716,627, “Solution-Dependent Regularization Method for Quantizing Continuous-Tone Lithography Masks.” In a post process, contours are extracted to obtain mask geometry from the final QTM.
Some embodiments additionally utilize a novel, more efficient data representation for the CTM and the target wafer pattern. In these embodiments, the grid points are 4 or 5 times sparser than existing measures and the data stored at each data point is minimal, yet the representation is accurate within the precision of the optical system being modeled. Added together, in some embodiments, the CTM and the target wafer pattern for the entire mask layer for optical (193i) projection of wafer lithography can be stored in the combined memory of all compute nodes of a currently commercially viable computational platform. When, in the future, EUV lithography requires ILT, a similarly commercially viable computational platform of that time can store the entire mask layer for EUV projection. ILT of EUV requires higher precision and therefore requires more memory to represent the data. In this disclosure, for ease of comprehension, the discussion uses the 193i mask situation where the entire mask layer is stored in the aggregate memory of the computing platform and is iteratively optimized together. The present disclosures are applicable for processing large sections of the entire mask layer even if the aggregate memory is insufficient to store the entire mask layer. In these embodiments, the CTM and the target wafer pattern for all tiles of the entire mask layer can be resident in memory at all times throughout processing the entire mask layer. This avoids time consuming nonresident memory access, whether solid-state drives or hard disk drives, enabling fast updates of the halo regions using distributed processing. The memory required to hold a large section is easily calculated as (X dimension/grid spacing)*(Y dimension/grid spacing)*(data size at each grid point). In some embodiments, intermediate results are only held in memory for the duration of the calculations within a tile.
Having the CTM and the target wafer function sample array for all tiles of the entire mask layer in memory at all times also enables the present embodiments to compute an optimization iteration for the entire mask layer at once, instead of optimizing each tile independently of each other, as is done in the art. As a result, the present embodiments eliminate stitching issues in a correct-by-construction manner, and compute the CTM for large sections, including entire mask layers, efficiently using a commercially viable computational platform.
In some embodiments, some MPC are performed during RET, where the mask is to be used in a lithographic process to form a pattern on a wafer.
In some embodiments, sampled values of smooth functions, which are continuous differentiable functions, on a grid and are represented in an array. In some embodiments, how well the predicted wafer pattern matches the target wafer pattern is represented as a smooth function. This technique obviates the need to find contour edges on the predicted wafer pattern and then compare them to contour edges on the target wafer pattern, as is done in most existing ILT implementations.
In some embodiments, MPC may take the ILT process down to the point where the number of areas that are left to need further optimization are few enough, and the tile containing such areas are sufficiently large to be statistically likely that optimizing those areas are not going to affect the neighbor's halo regions inside the tile. By understanding where such areas are throughout the design, a re-tiling of the design at such a stage may choose the tile size and area including potentially non-rectangular area or even curvilinear boundaries and corresponding halo regions along the perimeter.
In some embodiments, there may be iteration among different optimization strategies, for example, where the entire design is optimized all together in one strategy, and where tiles are optimized independently of each other in another strategy. The strategy may be pre-set, such as optimizing the entire design for a pre-set number of optimization iterations, then optimizing tiles until each tile meets the “cost criteria” (which may be hitting a maximum number of iterations allowed, or meeting some quality criteria, or failing to improve quality criteria sufficiently), then iterating the whole design again for another pre-set number of iterations. In another example, the strategy may be adaptive to some set of criteria observing the state of the mask design and the global and local optimization progress including the rate of change, and the rate of change of the rate of change, of the optimization criteria with various strategies being deployed with different parameters and potentially also different tiling as the ILT process proceeds.
Function Sample Arrays
The goal of RET is to create a mask such that the energy in the substrate is below a threshold everywhere that the substrate should be clear (or dark if negative resist is to be used), above the threshold everywhere the substrate should be dark (or clear for negative resist), and transition through threshold at the desired locations. In some embodiments, smooth functions are used to represent clear areas, dark areas, and transition locations. Smooth functions are continuous and differentiable. The smooth functions are captured on a grid sufficiently fine to define the functions within a tolerance. The array of values representing a smooth function shall be referred to in this disclosure as a Function Sample Array (FSA), which is an array of real, or possibly complex, values of the underlying function at sampling locations. In some embodiments, smooth functions are implemented as band limited functions, which are by nature infinitely differentiable. A band limited function is a function that only contains frequency components within a fixed limit as opposed to a theoretically infinite number of components. The nature of the band limited functions determines the sampling rate (grid spacing). The present embodiments uniquely recognize that light emanating from the mask and of the energy absorbed by the substrate are naturally represented by smooth functions. The target wafer pattern, the predicted wafer pattern, and the CTM are modeled as FSAs.
Leveraging knowledge of the optical lithography allows smooth functions to be chosen, such that the exact function can be defined on a grid much coarser than used in existing RET methods. The lithographic imaging resolution is based on a wavelength and a numerical aperture of the lithographic imaging system. In the present embodiments, an FSA grid has a plurality of grid points, and the grid points are spaced at a grid pitch. The grid pitch may be set by choosing a transition distance that is less than the lithographic imaging resolution of the lithographic imaging system and dividing the transition distance by a value such as from 3 to 6 or may be set based on pre-defined edge placement error specification. The determining factor on the divisor is the accuracy required when determining where the function crosses the threshold. The key to these embodiments is that the smooth function is accurately captured by its values at the grid points. This means that the predicted wafer pattern grid points can be compared directly to the target wafer pattern grid points without having to compute the exact location of the mask pattern contours. The ability to accurately represent a pattern with limited number of samples enables the computation of large tiles with less memory and higher speeds than conventional methods. This enables fast, exact, and distributed computation—which can, for example, be GPU-based—of differentiable cost functions that measure the degree of shape matching.
The present embodiments form grids based on the lithographic imaging system physics for all stages from the CTM to the target pattern FSAs and have the ability to resample reliably onto finer grids. Because of this, the present embodiments can work on large areas in a single compute node. Further, the present embodiments decompose computations of extremely large areas such as an entire mask layer for 193i masks into tiles without stitching artifacts. These possibilities have not been obvious to the reticle enhancement technology industry since there are multiple stumbling blocks to address, such as accurate grid-based pattern representation without ultrafine grids, and reliably interpolating to finer grids on the fly. For example, instead of using a 1-4 nm sampling grid for an RET of 193i lithography as is typical in the prior art, in the present embodiments a sampling grid of 8-10 nm scale can be used. This enlargement of the grid sampling saves 5× to 100× or more in required memory.
The FSA for the target wafer pattern is generated from the input target pattern. The FSA for the predicted wafer pattern is generated from the CTM using a lithography system model. The predicted wafer pattern FSA is massaged to have characteristics similar to the target pattern FSA, such as values near 1 inside a shape, near 0 outside a shape, and with smooth transitions between these regions. This massaging prevents a value of 0.15 in the predicted pattern being a mismatch for a value of 0.0 in the target pattern in clear (or dark in negative resist) areas. The only values that are critical are where the function transitions through the threshold. Therefore, when the values at the grid points of the predicted wafer pattern FSA match the values of the target wafer pattern FSA, the mask will accurately create the desired pattern on the substrate. The smooth function representations that are in an FSA support optimizing values without any explicit knowledge of edge locations in the target wafer pattern.
In step 230, a CTM 231 is calculated. The CTM 231 can be initialized with a first guess, such as a constant value, a low-pass filter applied to the target pattern, a previously determined CTM (e.g., a preliminary result previously computed), or a low-pass filtered mask obtained through other means (e.g., when addressing a hot spot in an existing mask design or examining a solution provided by another system).
In step 240, a predicted pattern FSA (representing a predicted wafer pattern) is calculated from the CTM and the system models.
In step 250, the target pattern FSA is compared to the predicted pattern FSA computed for the CTM. Comparison of the target pattern FSA and the predicted pattern FSA uses grid points of the pattern grid. The comparison may include calculating a cost density function using the target pattern function and the predicted pattern function. The predicted pattern function (FSA) may be generated using the CTM, a lithographic imaging system model, and a resist process model.
Step 260 for the present embodiments involves an optimization technique for the CTM of iterating on a proposed solution until the cost is reduced to as close to 0 as possible when the values at the equivalent grid points are compared for the predicted pattern FSA and the target pattern FSA.
In step 270, when the desired result is achieved, the proposed solution is captured as an optimized CTM, which is further regularized and transformed into a QTM.
Optimizing the CTM
The present embodiments utilize an optimization technique of iterating on a proposed solution until the desired result is achieved. The proposed solution is captured as the CTM, which is later transformed into a QTM in some embodiments. The measurement of the desirability is determined by comparing the FSAs for the predicted pattern and the target design pattern. The comparison of the FSAs involves comparing, perhaps within some tolerance, the values at the equivalent grid points representing the two functions. The goal of the process being described is to reduce the cost as close to 0 as possible. Other techniques are possible to converge using different cost metrics.
Step 320 includes inputting a target pattern (e.g., a target wafer pattern) to be formed on the substrate using the substrate lithography process, the target pattern being within a design area. In some embodiments, the target pattern comprises a plurality of patterns on a wafer, and the design area may comprise an entire mask layer or a large section of a mask layer of a semiconductor chip. In step 320, in some embodiments of the present disclosure, certain geometric manipulations of the target pattern may be performed. For example, edge bias that accounts for etching effects during the processing of the substrate may be precomputed prior to the optimization steps in steps 330 and later.
In step 330, a target pattern FSA is calculated for the target pattern, such as a target wafer pattern. In some embodiments, the calculating of the target pattern function includes applying a low-pass filter (which may also be referred to as a blurring) to the target pattern. The low-pass filter may be, for example, a Gaussian, or any other filter that is well-localized in space and frequency.
In step 340, a CTM (i.e., a proposed mask) is calculated, as explained in relation to step 230 of
In step 350, the substrate lithography system model is used to calculate a predicted pattern FSA that will be produced on the substrate by the CTM. In some embodiments, the calculation of the predicted pattern FSA (e.g., a predicted resist pattern function) can include calculating a projected image function from the CTM, using the substrate imaging system model. The projected image function and a resist process model are then used to calculate the predicted pattern FSA produced by the projected image function. The calculating of the projected image function may utilize a localized Fourier interpolation to go to a finer grid according to the needs of the calculation method or of subsequent use of the projected image.
In step 360, a cost is computed using the target pattern FSA and the predicted pattern FSA, and a functional derivative of the cost with respect to the CTM is also computed. The cost may be, for example, a total cost. The cost can be represented by a smooth function. In some embodiments, the costs may be global cost data, which can include, for example, local partial costs, cost densities, and cost gradients. In some embodiments, the computing of the functional derivative accounts for neighboring pattern information in a boundary area surrounding the design area. In some implementations, the computing of the cost includes calculating a cost density function using the target pattern function and the predicted resist pattern function and integrating the cost density function over the design area. The calculating of the cost density function can include squared differences between the target pattern function and the predicted resist pattern function, absolute values of these differences, or any formula that produces positive values that tend to zero where the patterns match and to larger numbers where they do not. These cost density values may also be weighted according to other information provided with the target pattern or derived from the target pattern. For example, the weights may be used to emphasize fitting edges and deemphasize matching corners.
In step 370, the cost and the functional derivative are compared to cost criteria. In other words, this comparison determines a mismatch between the predicted and desired patterns. The cost criteria can include converging the cost to a value near a minimum, or minimizing the magnitude of the functional derivative, or its components. That is, the cost criteria can be deemed to be met when further iterations do not vary from previous solutions by more than a certain amount. The cost criteria in some embodiments can include evaluating a distribution of values of the cost density function over the design area. The cost criteria can also be defined as an amount of mismatch, for example, a specified acceptable amount, such as a geometrical value or a percentage.
Note that in flowchart 300, variations are possible. For example, steps 310 and 320 are interchangeable in sequence. Step 330 can be a null-step in some embodiments of the present disclosure. Steps 340 and 350 may be combined in one step. In steps 360 and 370, computing the derivative is optional. Other computations could be done in steps 360 and 370 to help iteration on the CTM.
In some approaches, a target pattern function with more distinct edges can be generated prior to the computing of the cost of step 360, by applying a soft thresholding function in step 335 to the target pattern function to sharpen the edges of the target pattern function. The soft-thresholding turns the encoded patterns into higher resolution functions that are featureless away from the edge transitions, thus giving more weight to the contours without the need to determine them directly. This allows the target pattern function to be stored at lower grid resolution than when used for making comparisons. The cost, such as a total cost, is computed in step 360 using the target pattern FSA after any applied sharpening and the predicted resist pattern function.
In an example of thresholding the target pattern FSA, the target pattern FSA in step 330 is generated by applying a low-pass filter to the target pattern, such that the target pattern function is band-limited to a bandwidth of the low-pass filter. The target pattern function is sampled on a first pattern grid having a first sampling rate that may be at or higher than the Nyquist rate for this bandwidth, and the thresholded target pattern function that is generated in step 335 is sampled on a second pattern grid having a second sampling rate that is higher than the first sampling rate. The soft thresholding function may be, for example, a sigmoidal function that sharpens transitions between minimum and maximum values in the target pattern. For example, the slope of the thresholded target pattern function may be increased in transitions between minimum and maximum values in the target pattern, thus sharpening the edges of the target pattern function.
Soft thresholding enables the function to more closely conform to results of the predicted resist pattern function. Soft thresholding can be implemented as mapping 0 to “0” (soft range), 1 to “1”, a threshold value to a threshold value (e.g., ½ to “½”); and can be implemented as a smooth, monotonically increasing switching function based on the Gaussian error function, the hyperbolic tangent, or any other sigmoidal function one of ordinary skill may devise. In some embodiments, this first soft thresholding function can also be applied to the predicted resist pattern function to generate a second predicted resist pattern function for comparison to the target pattern.
Returning to step 380 of
Legalization
In the present disclosure, a CTM can be transformed to a reliably manufacturable mask. Modifications can be made to the CTM and/or to the QTM to ensure that the mask is manufacturable.
In some embodiments, the iterative optimization of the CTM uses costs related to reliable manufacturability of the mask shapes. In some embodiments, a set of constraints related to reliable manufacturability of the mask shapes prohibit certain shapes to be considered. In some embodiments, after the cost criteria is met, mask shapes may be further modified to fit the exact specifications for mask manufacturability. Costs and criteria for mask manufacturability include, but are not limited to, minimum size and spacings, maximum curvature allowed, minimum dose margin and mask edge error factor (MEEF). Optimization of MEEF and other factors are disclosed in U.S. Pat. No. 8,719,739, “Method and System for Forming Patterns Using Charged Particle Beam Lithography,” which is owned by the assignee of the present application.
The CTM has a continuous range of values that must be converted to contiguous regions of allowed transmission values. The contiguous regions of fixed transmission value correspond to shapes on a manufacturable mask. The allowed transmission values depend on the type of mask; for example, they are conventionally 0 or 1 for a chrome-on-glass mask, or −√{square root over (0.06)} and 1 for a 6% attenuated phase shift mask.
In an embodiment, this conversion is accomplished through regularization, which involves adding terms to the cost or cost function, that favor manufacturable masks.
The primary regularization needed is to favor masks that are very close to the allowed transmission values everywhere, with a possible exception for transitions from one allowed value to another, which may contain intermediate values. In an embodiment, a term, which shall be referred to as a “value-shaping term,” is introduced that favors the allowed values and favors short transitions between a region of one value to a bordering region of another value.
A CTM that is selected using a value-shaping term in the optimization may contain shapes that will be difficult to manufacture reliably. In an embodiment, a second value-shaping term is introduced that favors shapes that will have good dose margin when manufacturing the mask. Such a term may use a PSF to measure how much the shapes change and compute a cost based on the changes.
A large set of theoretical masks can provide good lithographic results on a wafer. Regularization selects from the subset of masks that can be manufactured, with a preference for those that can be reliably manufactured. A total cost system can be utilized to penalize masks that cannot be made while optimizing to reduce manufacturing penalty and while retaining good wafer results.
Distributed Processing
An aspect of the present embodiments is the combination of data representations as FSAs as captured on a regular grid, which efficiently delivers and receives data from each process of a distributed process.
As stated previously, in order to predict the mask pattern for the CTM and compare the predicted wafer pattern that the CTM produces to the target wafer pattern, the present embodiments decompose the design into tiles, or large sections of the mask layer. Although the present embodiments of optimizing an entire design through distributed processing shall be described first in terms of a CTM and finally as a QTM, the embodiments can also be applied to types of proposed masks other than the CTMs and QTMs described herein. In some embodiments, the proposed mask for a single tile, first represented as a CTM and later represented as a QTM, and the corresponding target wafer pattern for that section of the design are held in memory on a single node.
Segments of the FSA can be sampled at a higher rate when computations are being performed on specific tiles within the entire design. For example, the entire pattern can be divided into a plurality of tiles, and calculations on the plurality of tiles are performed in distributed processes. Distributed processes operate independently, and many processes can run at the same time. In some embodiments, a single tile is processed on a compute node of a computing cluster. That cluster may hold other nodes operating on other tiles in parallel. In any tile of the plurality of tiles, the CTM, the predicted pattern FSA that it produces, and the target pattern FSA are delivered at the design-wide grid spacing, but when more detailed calculations are required, the values of the FSAs can be calculated at any spacing. The results of the distributed process are returned on the design-wide grid spacing. That is, the sampling rate can be increased for higher resolution calculations when computations are being performed on a particular region of the tile, but the additional values (higher sampling rate) of the FSA do not need to be stored in memory during the computation of the entire pattern. This saves memory and enables an entire mask layer to be computed in tiles using independent distributed processes. The up-sampling may be performed by taking the discrete Fourier transform via Fast Fourier Transform (FFT) algorithms, extending the transform to higher frequencies corresponding to the higher sampling rate via periodic extension, multiplying the result by the low-pass filter in frequency space corresponding to the ideal filter multiplied by a localizing Gaussian in real space, and applying the inverse discrete Fourier transform via FFT algorithms. Stitching errors between tiles can be reduced to the point of elimination by adding more to the boundary of the tiles so that the mismatch occurs a prescribed number of Gaussian widths away from the tile edge. The foregoing describes the use of a Gaussian localizing factor, but other forms that limit spatial extent may be suitable as known to one skilled in the art. The sampling rates are also set higher than the Nyquist minimum rate so that the function bandwidth stays within the flat part of the filter in frequency space and to a prescribed accuracy.
The present methods enable graphical processing unit (GPU) acceleration due to regular grid-structured computations. The FSAs are conducive to GPU computations because many grids can be processed simultaneously. The computations involve single instruction, multiple data (SIMD) operations, with no contour-chasing. Exact function resampling is achieved via highly optimized FFTs. GPU computation time is greatly reduced due to reduction in data transfer time, since the amount of grid sample data that needs to be held in memory is based on using only the coarsest grid necessary to exactly represent the functions, and because in some embodiments the iterations associated with each tile can be computed on a compute node comprised of one or more GPUs. The minimization of data transfer to/from the GPU is important because a GPU is extremely fast at computing but typically limited by its data transfer rate. The present methods increase the area of a tile that can fit in a given memory size by 4 to 10 times compared to conventional methods, with a corresponding 5× to 10× reduction in overhead and 5× to 10× reduction in seams between tiles.
Use of localized Fourier interpolation via FFTs and a localization function that confines the effects of mismatched boundaries to a specified distance allows computations to operate on whatever resolution grid is most appropriate, and only store quantities that persist through the optimization on their minimum grids. Without this, the memory requirements become impossible to meet for calculating a mask layer for an entire tile on a single node. Another benefit of the present methods is that the computation of the cost function and its derivatives is distributed using large tiles with sufficient overlap to allow for the lithographic imaging proximity range and the localized Fourier interpolation range, while still optimizing all the mask parameters over the entire tile without stitching artifacts when the tiles are reassembled.
In some embodiments, using decomposition into tiles with their respective halos, independent evaluation of each tile's contribution to the cost functional and derivatives can be performed, and the benefits of band-limited, smooth functions allow a single node to hold values for a large design area due to memory efficiency. Tiling the entire design also enables computation acceleration, such as using GPUs, which is further enabled by regular grid-based computations and leverage from FFTs as needed.
Optimizing the Entire Design
In
Each iteration also includes step 541 of collecting the costs and the derivative data for all tiles in the plurality of tiles to calculate a cost for the entire design area. In some embodiments, the collected costs include costs for reliable manufacturability of the mask as discussed in step 360 and 395. If the cost does not meet the cost criteria in step 551, the costs and the derivative data are further iterated to modify the proposed mask in step 561. Step 551 corresponds to steps 370 and 380 of
In some embodiments, each tile has a halo region surrounding the tile; the calculating is calculated for every tile and its halo region; and each iteration further includes updating the CTM for an individual tile in the subset of tiles, after calculating the predicted wafer pattern, and using the updated CTM for the individual tile to update the halo regions of tiles that neighbor the individual tile. In certain embodiments, the halo region for a tile in the plurality of tiles has a thickness surrounding the tile that is as small as 1.5 to 4 times a lithographic imaging proximity range cutoff of a substrate lithography system for the RET.
In some embodiments, the calculating of every tile is performed on a computing node accelerated by a graphical processing unit. In some embodiments, the representing of the target wafer pattern as a FSA includes applying a low-pass filter to the target wafer pattern. In some embodiments, the FSA for the target wafer pattern is band-limited to a spatial frequency cutoff of a substrate lithography system, and optionally may be sampled on a grid that meets a Nyquist criterion. In some embodiments, the target wafer pattern is for a mask layer of a semiconductor chip.
Seeding the Proposed Mask with Deep Learning
In a deep learning neural network 620 (
Training data is not repetitive (unlike designs) and includes many variations on a pattern, e.g., rotations and sub-pixel translations as well as data intentionally below a minimum feature threshold for learning boundary conditions. In some embodiments training data includes sweep-based patterns with varying width and spacing. In other embodiments, training data includes constrained random patterns with varying angle, width and spacing. Each pattern in the training data includes a halo to allow for sample points to go beyond the data boundary.
The predicted mask or QTM 750 that is output in
In an embodiment, the architecture for each of the trained neural networks 820 and 840 are the same. However, during training each neural network system may use different loss functions. The training method shown in
In an embodiment the optimization may include MRC. The QTM may be used to generate a predicted wafer pattern during optimization; i.e., the retraining may further comprise calculating a predicted wafer pattern using the refined QTM. Then in a post-process step 860 the refined QTM 850 is corrected for MRC using flowchart 300 with an MRC gradient cost function similar to cost function in steps 360 and 370 in flowchart 300 of
The first trained neural network 820 and second trained neural network 840 may comprise a U-net, such as described in
Computation Systems
The computation and processing steps described in this disclosure may be implemented using general-purpose computers with appropriate computer software as computation devices. Multiple computers or processor cores may also be used in parallel. In some embodiments, a special-purpose hardware device, either used singly or in multiples, may be used to perform the computations of one or more steps with greater speed than using general-purpose computers or processor cores. In certain embodiments, the special-purpose hardware device may be a graphics processing unit (GPU). In other embodiments, other special-purpose hardware devices may be used as co-processors, such as a Digital Signal Processor (DSP), a Tensor Processing Unit (TPU), a Field-Programmable Gate Array (FPGA), or an Application-Specific Integrated Circuit (ASIC).
The master node 1010 and viewing node 1020 may be connected to network file system 1030 and GPU-enabled nodes 1040 via switches and high-speed networks such as networks 1050, 1052 and 1054. In an example embodiment, networks 1050 can be a 56 Gbps network, 1052 can be a 1 Gbps network and 1054 can be a management network. In various embodiments, fewer or greater numbers of these networks may be present, and there may be various combinations of types of networks such as high and low speeds. The master node 1010 controls the CDP 1000. Outside systems can connect to the master node 1010 from an external network 1060. In some embodiments, a job is launched from an outside system. The data for the job is loaded onto the network file system 1030 prior to launching the job, and a program is used to dispatch and monitor tasks on the GPU-enabled nodes 1040. The progress of the job may be seen via a graphical interface, such as the viewing node 1020, or by a user on the master node 1010. The task is executed on the CPU using a script which runs the appropriate executables on the CPU. The executables connect to the GPUs, run various compute tasks, and then disconnect from the GPU. The master node 1010 can also be used to disable any failing GPU-enabled nodes 1040 and then operate as though that node did not exist.
In some embodiments, a system for reticle enhancement technology includes a computer processor configured to receive a target wafer pattern to be used in reticle enhancement technology; and calculate a function sample array (FSA) for the target wafer pattern, the FSA for the target wafer pattern being a smooth function. The computer processor is also configured to calculate a continuous tone mask (CTM), where the CTM is represented as a smooth function captured as a function sample array (FSA); and to compare the target wafer pattern to a predicted wafer pattern produced by the CTM. In further embodiments, the target wafer pattern is divided into a plurality of tiles, and the computer processor is further configured to compute a cost and derivative data for each tile in the plurality of tiles, the computing of the plurality of tiles being performed in a distributed process. The cost and the derivative data are based on comparing the target wafer pattern and the predicted wafer pattern produced by the CTM.
In some embodiments, a system for reticle enhancement technology comprises one or more computer processing devices configured to perform the steps described herein. For example, the system may include a) a device configured to input a target wafer pattern, the target wafer pattern spanning an entire design area; b) a device configured to divide the entire design area into a plurality of tiles, each tile having a halo region surrounding the tile; and c) a device configured to calculate an optimized mask, wherein the optimized mask is generated by a first trained neural network using the target wafer pattern, wherein the calculating is performed for each tile in the plurality of tiles including its halo region. The devices of a), b) and c) may be one single device (e.g., one computer processor) or more than one device (e.g., more than one computer processor, or a computer cluster, where each computer processor performs one or more of a), b) and c)).
In some embodiments, a system for reticle enhancement technology comprises a computer cluster configured to a) receive a target wafer pattern, the target wafer pattern spanning an entire design area; and b) calculate an optimized mask, wherein the optimized mask is generated by a trained neural network using the target wafer pattern.
In general embodiments, the system is a computer processor, which in some embodiments can include graphical processing units or other co-processors for performing distributed computation, such as parallel processing. In some embodiments, the graphical processing units or other co-processors may be configured to interconnect with each other for fast communication. The computer processor is configured to receive a target pattern to be used in reticle enhancement technology, and generate a target pattern function for the target pattern, where the target pattern function is a FSA. The computer processor is also configured to generate a CTM and compare the target pattern function to a predicted pattern function produced by the CTM. The CTM is a smooth function. The computer processor is also configured to generate an optimized QTM using a neural network, wherein the QTM is converted from the CTM before optimization.
Reference has been made in detail to embodiments of the disclosed invention, one or more examples of which have been illustrated in the accompanying figures. Each example has been provided by way of explanation of the present technology, not as a limitation of the present technology. In fact, while the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, it is intended that the present subject matter covers all such modifications and variations within the scope of the appended claims and their equivalents. These and other modifications and variations to the present invention may be practiced by those of ordinary skill in the art, without departing from the scope of the present invention, which is more particularly set forth in the appended claims. Furthermore, those of ordinary skill in the art will appreciate that the foregoing description is by way of example only, and is not intended to limit the invention.
This application is a continuation-in-part of U.S. patent application Ser. No. 18/175,313, filed on Feb. 27, 2023, and entitled “Methods for Modeling of a Design in Reticle Enhancement Technology”; which is a continuation of U.S. patent application Ser. No. 17/652,881, filed on Feb. 28, 2022, issued as U.S. Pat. No. 11,620,425, and entitled “Methods for Modeling of a Design in Reticle Enhancement Technology”; which is a divisional of U.S. patent application Ser. No. 17/248,325, filed on Jan. 20, 2021, issued as U.S. Pat. No. 11,301,610 and entitled “Methods for Modeling of a Design in Reticle Enhancement Technology”; which is a continuation-in-part of U.S. patent application Ser. No. 15/930,774, filed on May 13, 2020, issued as U.S. Pat. No. 10,909,294 and entitled “Modeling of a Design in Reticle Enhancement Technology; which is a continuation of U.S. patent application Ser. No. 15/853,311, filed on Dec. 22, 2017, issued as U.S. Pat. No. 10,657,213 and entitled “Modeling of a Design in Reticle Enhancement Technology”; all of which are hereby incorporated by reference in their entirety.
| Number | Date | Country | |
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| Parent | 17248325 | Jan 2021 | US |
| Child | 17652881 | US |
| Number | Date | Country | |
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| Parent | 17652881 | Feb 2022 | US |
| Child | 18175313 | US | |
| Parent | 15853311 | Dec 2017 | US |
| Child | 15930774 | US |
| Number | Date | Country | |
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| Parent | 18175313 | Feb 2023 | US |
| Child | 18515140 | US | |
| Parent | 15930774 | May 2020 | US |
| Child | 17248325 | US |
