The present disclosure relates to a module.
In recent years, with the increasing number of components in an electronic device such as smart phone as well as the reduction in size and height of the electronic device, there arises a problem of noise interference between electronic components used in the electronic device. To address this problem, it is required to form an electromagnetic shield film on a module product used for communication. Such a shield film can be electrically connected to a conductor exposed on a side surface of a circuit board in the module, to thereby exhibit a shielding effect. Generally, the shield film is electrically connected to a conductor at a ground potential that is exposed on the side surface of the circuit board.
Japanese Patent Laying-Open No. 2018-88460 (PTL 1) discloses an example of the module having a shield film (shield layer) that blocks unnecessary electromagnetic waves to electronic components mounted on a circuit board. In this module, a plurality of electronic components are mounted on one main surface of the circuit board, and a sealing resin layer is applied to seal these electronic components. This module includes a first shield layer covering an upper surface and a side surface of the sealing resin layer as well as a side surface of the circuit board, and a second shield layer covering a partial region of the other main surface of the circuit board and a side surface of the first shield layer.
PTL 1: Japanese Patent Laying-Open No. 2018-88460
While the configuration disclosed in PTL 1 has two types of shield layers to shield electromagnetic waves, this shielding is not sufficient.
In view of this, an object of the present disclosure is to provide a module that enables sufficient shielding against electromagnetic waves, while ensuring a certain degree of freedom in designing the internal configuration of a substrate.
In order to achieve the above object, a module based on the present disclosure includes: a substrate having a first surface and a second surface; an electronic component mounted on the first surface; a sealing resin disposed to cover the first surface and the electronic component; a shield film covering an upper surface and a side surface of the sealing resin and covering a side surface of the substrate; a lowermost layer ground conductor disposed on the second surface; and an internal ground conductor located within the substrate, separated from the second surface, and disposed to be electrically connected to the shield film at the side surface of the substrate. The lowermost layer ground conductor includes portions different in width from each other as seen in a direction perpendicular to the second surface. With the lowermost layer ground conductor and the internal ground conductor seen in the direction perpendicular to the second surface, a region occupied by the internal ground conductor is included in a region occupied by the lowermost layer ground conductor.
According to the present disclosure, the lowermost layer ground conductor extends, at any position along one side, from the side of the substrate inwardly to a great extent, and therefore, electromagnetic waves can be shielded sufficiently while ensuring a certain degree of freedom in designing the internal configuration of the substrate.
Any dimensional ratio shown in the drawings does not necessarily represent the exact actual dimensional ratio, but may be exaggerated for convenience of illustration. In the following description, the concept “top/upper” or “bottom/lower” mentioned herein does not necessarily refer to the exact “top/upper” or “bottom/lower,” but may refer, in a relative sense, to “top/upper” or “bottom/lower” of a posture shown in a drawing(s).
Referring to
Module 101 includes: a substrate 1 having a first surface 1a and a second surface 1b; an electronic component 3a mounted on first surface 1a; a sealing resin 6 disposed to cover first surface 1a and electronic component 3a; a shield film 8 covering an upper surface and a side surface of sealing resin 6 and covering a side surface of substrate 1; a lowermost layer ground conductor 21 disposed on second surface 1b; and an internal ground conductor 23 located within substrate 1, separated from second surface 1b, and disposed to be electrically connected to shield film 8 at the side surface of substrate 1. First surface 1a and second surface 1b are respectively a front side and a back side relative to each other. In addition to electronic component 3a, electronic components 3b, 3c are also mounted on first surface 1a. Lowermost layer ground conductor 21 is electrically connected to shield film 8.
Electronic components 3a to 3c are mounted by means of a pad electrode 18 formed on first surface 1a. A conductor pattern 16 is disposed within substrate 1. Conductor pattern 16 forms at least a part of a signal line. Substrate 1 includes an insulating layer 2. Substrate 1 may be a multilayer substrate. The material for insulating layer 2 may be ceramic or resin, for example. Substrate 1 is formed by stacking a plurality of insulating layers into a single substrate. A conductor via 15 is also located within substrate 1. Conductor via 15 is used to electrically connect conductor patterns at different heights to each other. The signal line is formed by appropriately combining conductor via 15 and conductor patterns 16.
An external terminal 17 and a ground terminal 19 are formed on second surface 1b of substrate 1. Second surface 1b is mostly covered with a resist film 20. External terminal 17 includes a pad electrode and a solder disposed on the surface of the pad electrode. By the presence of this solder, external terminal 17 protrudes from the surface of resist film 20. The solder disposed in such a way on the surface of the pad electrode is not a requisite part. No solder may be attached to the surface of the pad electrode.
The right side as seen in
In any of the first to third examples of the shape of internal ground conductor 23 shown herein, at any position along first side 81, with lowermost layer ground conductor 21 and internal ground conductor 23 seen in the direction perpendicular to second surface 1b, the region occupied by internal ground conductor 23 is included in the region occupied by lowermost layer ground conductor 21. In other words, when any point is selected on internal ground conductor 23, lowermost layer ground conductor 21 is always present at the position onto which the selected point is projected perpendicularly. As seen in the direction perpendicular to second surface 1b, internal ground conductor 23 never extends beyond lowermost layer ground conductor 21. The fact that Region A is “included” in Region B also refers to the fact that Region A is identical to Region B. A simplified model is described later herein.
According to the present embodiment in which the module is configured to have lowermost layer ground conductor 21 that is not constant in width, lowermost layer ground conductor 21 extends, at any position along first side 81, from the side of substrate 1 inwardly to a great extent, and therefore, electromagnetic waves can be shielded sufficiently while ensuring a certain degree of freedom in designing the internal configuration of substrate 1. Internal ground conductor 23 extends to a smaller extent than lowermost layer ground conductor 21, and therefore, a greater space can be ensured for arranging interconnections for example in substrate 1, which ensures the degree of freedom of design.
As illustrated in connection with the present embodiment, preferably lowermost layer ground conductor 21 has opening 21a or a recess 21k in which a signal line is to be disposed, and lowermost layer ground conductor 21 is separated from the signal line. At the height of lowermost layer ground conductor 21, the signal line is formed as external terminal 17, and therefore, lowermost layer ground conductor 21 is separated from external terminal 17.
As illustrated in connection with the present embodiment, preferably resist film 20 partially covers lowermost layer ground conductor 21, and resist film 20 has opening 20b for exposing a part of lowermost layer ground conductor 21. This configuration can be employed to clearly separate terminals from each other by resist film 20, when the module is mounted on a mother board or the like by a solder, and thereby prevent the solder from flowing to another terminal and thereby causing short circuit.
The presence of resist film 20 is not a requisite condition. The module may have a configuration with no resist film 20 covering the surface of lowermost layer ground conductor 21 for example.
Description with Simplified Model
For the sake of facilitating understanding, the following description is given with reference to a further simplified model.
First, a lowermost layer ground conductor having a recess is described.
Another example may be the one as shown in
Next, a lowermost layer ground conductor having an opening is described.
A still another example may be the one as shown in
A further example may be the one as shown in
Thus, lowermost layer ground conductor 21 is configured to be inconstant in width and include portions different in width from each other. In this way, improvement in the degree of freedom in arranging terminals on the bottom surface which is a surface of the module to be mounted, and/or increase in the number of terminals for signal lines, for example, can be achieved.
To fabricate the module according to the present embodiment, firstly a mass substrate of a large size including a plurality of modules is prepared, electronic components are mounted as required on the surface of the mass substrate, and thereafter a resin is molded to seal these electronic components. Resin molding may be done by any method such as transfer molding, compression molding, or dipping of liquid resin, for example. After molding the resin, the mass substrate is separated into pieces by any means such as dicer, laser, or scribing, for example. In this way, individual substrate 1 having its surface on which an electronic component(s) is mounted and covered with sealing resin 6 is obtained.
In order to expose lowermost layer ground conductor 21 and internal ground conductor 23 from the side surface of substrate 1, a conductor pattern having a shape corresponding to the shape of these conductors may be disposed in advance on the surface of or inside the mass substrate, such that a cross section of the conductor pattern is exposed from a side surface generated newly as a result of separation of the mass substrate into pieces of the size of individual modules.
In order to electrically connect, at the side surface of substrate 1, shield film 8 to lowermost layer ground conductor 21 and internal ground conductor 23, the mass substrate may be separated into pieces of the size of individual modules, and thereafter spattering may be performed with the side surface of substrate 1 exposed, to thereby form shield film 8.
Referring to
Only conductor patterns disposed in a middle layer, not the lowermost layer, of substrate 1 are shown in
As illustrated in connection with the present embodiment, preferably lowermost layer ground conductor 21 is disposed along the entire periphery of substrate 1.
As illustrated in connection with the present embodiment, the presence of lowermost layer ground conductor 21 disposed along the entire periphery of substrate 1 enables sufficient shielding of electromagnetic waves.
More than one of the above-described embodiments may be employed in an appropriate combination.
The above embodiments disclosed herein are given by way of illustration in all respects, not by way of limitation. The scope of the present disclosure is defined by claims, and encompasses all modifications and variations equivalent in meaning and scope to the claims.
1 substrate; 1a first surface; 1b second surface; 2 insulating layer; 3a, 3b, 3c electronic component; 6 sealing resin; 8 shield film; 15 conductor via; 16 conductor pattern; 17 external terminal; 18 pad electrode; 19 ground terminal; 20 resist film; 20a, 20b opening (of the resist film); 21 lowermost layer ground conductor; 21a opening (of the lowermost layer ground conductor); 21k recess (of the lowermost layer ground conductor); 23 internal ground conductor; 23a opening (of the internal ground conductor); 23k recess (of the internal ground conductor); 23n discontinued portion (of the internal ground conductor); 71 first point; 71e, 72e point; 72 second point; 81 first side; 101, 102 module
Number | Date | Country | Kind |
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2019-237074 | Dec 2019 | JP | national |
This is a continuation of International Application No. PCT/JP2020/045594 filed on Dec. 8, 2020 which claims priority from Japanese Patent Application No. 2019-237074 filed on Dec. 26, 2019. The contents of these applications are incorporated herein by reference in their entireties.
Number | Date | Country | |
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Parent | PCT/JP2020/045594 | Dec 2020 | US |
Child | 17805883 | US |