Patent Grant
9087923
The present invention relates to a monolithic compound semiconductor structure, and in particular, to a monolithic compound semiconductor structure integrating a heterojunction bipolar transistor (HBT), a field effect transistor (FET), and a thyristor for applications in electrostatic discharge (ESD) protection circuits.
When a human body touches an integrated circuit, the accumulated electrostatic charges pass from the human body to the integrated circuit through the pins, and then the integrated circuit is discharged through the ground contact. The discharging process may produce a current of several amps within a few nanoseconds, leading to device degradation or damage. Therefore it is necessary to design an ESD protection system for the devices in an integrated circuit to sustain ESD events.
In monolithic compound semiconductor structures, ESD protection circuits are usually composed of p-n junction diodes or Schottky diodes due to the restriction caused by the vertically stacked layer structure. To achieve a high ESD protection level, several diodes connected in series are necessary and a larger die area is required. Besides, the turn-on voltage of a diode is small, which in turn limits the ESD protection level.
A silicon-controlled rectifier (SCR), also known as a thyristor, is a solid-state device with a four-layer pnpn structure commonly used in silicon integrated circuits. A SCR has a high turn-on voltage and a low holding voltage. When used in an ESD protection circuit, the SCR can clamp the voltage of the circuit in a lower level, such that the circuit can be effectively protected.
To achieve better device integration on a chip, a so-called BiHEMT structure that combines an HBT and an FET (or a high-electron-mobility transistor; HEMT) in a vertically stacked epitaxial structure has recently been developed for monolithic integrations of compound semiconductor devices. The HBT has either an npn or a pnp junction, while the FET/HEMT can be either n-type or p-type. If a four-layer pnpn junction can be formed in a BiHEMT structure, an epilayer structure that combines an SCR and a BiHEMT becomes possible. This can improve the ESD protection level while keeping the device area minimal.
The main object of the present invention is to provide a monolithic compound semiconductor structure, in which a n-type etching-stop layer and a p-type insertion layer are included in a BiFET structure, so that the epitaxial structure of an FET, an HBT, and a thyristor can be integrated in a compound semiconductor monolithic chip. The thyristor therein can be used in an ESD system. The surface area of a chip herewith is significantly reduced comparing with a conventional ESD system using diodes. Furthermore, the ESD performance can be improved, and thus the product competitiveness can be increased.
To reach the objects stated above, the present invention provides a monolithic compound semiconductor structure, which comprises a substrate, an FET epilayer structure, an n-type etching-stop layer, a p-type insertion layer, and an HBT epilayer structure. The FET epilayer structure is disposed on the substrate, comprising a channel layer and an n-type doped layer, in which the n-type doped layer is disposed on the channel layer, forming an n-type FET. The HBT epilayer structure comprises sequentially from top to bottom a sub-collector layer, a collector layer, a base layer, and an emitter layer. The sub-collector layer, the collector layer, and the emitter layer are n-type doped layers and the base layer is a p-type doped layer, and hence they form an npn HBT epilayer structure. The FET epilayer structure, the n-type etching-stop layer, the p-type insertion layer, and the sub-collector layer, the collector layer, and the base layer of the HBT epitaxial structure can be used to form a thyristor epitaxial structure with a pnpn junction.
In implementation, the n-type etching-stop layer described previously is formed of InGaP. The doping concentration in the n-type etching-stop layer is ranging from 1×1015 cm−3 to 1×1022 cm−3, and the thickness of said n-type etching-stop layer is between 50 Å to 5000 Å.
In implementation, the p-type insertion layer described previously comprises one or multiple p-type doped layer. The doping concentrations in neighboring p-type doped layers in the p-type insertion layer are different to each other. The doping concentration in each p-type doped layer of the p-type insertion layer is ranging from 1×1015 cm−3 to 1×1022 cm−3, and the thickness of each p-type doped layer of said p-type insertion layer is between 500 Å and 20000 Å.
In implementation, the p-type insertion layer described previously comprises a p+ doped layer and a p− doped layer. The p+ doped layer is a heavily doped p-type layer, and the p− doped layer is a lightly doped p-type layer. The p− doped layer is formed on said p+ doped layer.
In implementation, the p+ doped layer and the p− doped layer described previously are formed of GaAs.
In implementation, the doping concentration of the p+ doped layer described previously is ranging from 1×1018 cm−3 to 1×1022 cm−3, and the thickness of the p+ doped layer is between 1000 Å and 2000 Å.
In implementation, the doping concentration in the p− doped layer described previously is ranging from 1×1016 cm−3 to 1×1017 cm−3, and the thickness of the p− doped layer is between 2500 Å and 15000 Å.
In implementation, the FET epitaxial structure described previously is an n-type metal semiconductor FET (MESFET) epitaxial structure.
In implementation, the FET epitaxial structure described previously is an n-type high electron mobility transistor (HEMT) epitaxial structure.
In implementation, the FET epitaxial structure described previously is an n-type pseudomorphic high electron mobility transistor (pHEMT) epitaxial structure.
In implementation, the substrate described previously is formed of GaAs or InP.
For further understanding the characteristics and effects of the present invention, some preferred embodiments referred to drawings are in detail described as follows.
The monolithic compound semiconductor structure integrating the epitaxial structure of an FET, an HBT, and a thyristor provided by the present invention is shown schematically in
In implementation, the FET epitaxial structure 110 can be an n-type metal semiconductor FET (MESFET), an n-type high electron mobility transistor (HEMT), an n-type pseudomorphic high electron mobility transistor (pHEMT), or any n-type FET of other types. The n-type etching-stop layer 121 is formed preferably of InGaP. The doping concentration in the n-type etching-stop layer 121 can be ranging from 1×1015 cm−3 to 1×1022 cm−3 preferably in the range from 1×1017 cm−3 to 1×1018 cm−3. The thickness of the n-type etching-stop layer 121 is between 50 Å to 5000 Å, preferably from 100 Å to 500 Å. The p-type insertion layer 122 can comprise one or multiple p-type doped layers. The doping concentrations in p type doped layers neighboring the p-type insertion layer 122 are different to each other. The doping concentration in each p type doped layer of the p-type insertion layer 122 is ranging from 1×1015 cm−3 to 1×1022 cm−3, and the thickness of each p-type doped layer is preferably between 500 Å and 20000 Å. The HBT epitaxial structure 130 is made preferably of GaAs. The doping concentration in the sub-collector layer 131 can be ranging from 1×1015 cm−3 to 1×1022 cm−3, preferably a high doping concentration ranging from 1×1018 cm−3 to 1×1022 cm−3. When employing in a semiconductor device, as shown in
Table 1 shows an embodiment of a monolithic compound semiconductor structure provided by the present invention. In the embodiment a substrate and 14 epitaxial layers above a substrate are included. The first and the second layers from top to bottom are a heavily doped emitter contact layer and a cap layer. The third to the sixth layers are emitter layers which comprises multiple n-type doped layers of different thickness and doping concentration. The seventh layer is a base layer, which is a heavily doped p-type layer. The eighth to the tenth layers are an n-type doped collector layer and an n+ sub-collector layer. The eleventh and the twelfth layers are p-type doped layer, which is a p+ doped layer and a p− doped layer formed of GaAs. The p+ doped layer is a heavily doped p-type layer and the p− doped layer is a lightly doped p-type layer disposed on the p+ doped layer. The doping concentration in the p+ doped layer can be selected to be ranging from 1×1018 cm−3 to 1×1022 cm−3, and its thickness can be ranging from 1000 Å to 20000 Å. In this embodiment, the doping concentration in the p+ doped layer is selected to be 1×1018 cm−3 and the thickness is selected to be 1000 Å. The doping concentration in the p− doped layer can be ranging from 1×1016 cm−3 to 1×1017 cm−3, and its thickness can be ranging from 2500 Å to 15000 Å. In this embodiment, the doping concentration in the p− doped layer is selected to be 1×1016 cm−3 and the thickness is selected to be 2500 Å. The thirteenth layer is an n-type etching-stop layer formed of InGaP. Its doping concentration is selected to be 3×1017 cm−3, and its thickness is selected to be 200 Å. The fourteenth layer is an n+ layer. Its doping concentration is selected to be 4×1018 cm−3, and its thickness is selected to be 4000 Å. The structure from the seventh to the fourteenth layers is a pnpn structure and can be used to form a thyristor.
The ESD protection performance of a semiconductor integrated circuit can be characterized by using the transmission line pulse (TLP) testing, in which high current pulses are applied to the tested circuit. An I-V curve of the tested circuit can be obtained by analyzing the incident and reflected pulses. The energy range and the pulse width of the incident high current pulses are similar to the human body model (HBM).
To sum up, the present invention can indeed get its anticipated object to provide a monolithic compound semiconductor integrating the epitaxial structure of an FET, an HBT, and a thyristor. The thyristor made of the monolithic structure provided by the present invention can be applied in ESD protection circuits. The required area for an ESD circuit can therefore be significantly reduced. Furthermore, the higher trigger voltage, the lower holding voltage, the lower power dissipation, and the higher current handling capability of a thyristor considerably improve the performance of ESD protections. Besides, the fabrication process of the present invention is compatible with the current fabrication processes of BiHEMT technologies, and therefore the production cost can be significantly reduced.
The description referred to the drawings stated above is only for the preferred embodiments of the present invention. Many equivalent local variations and modifications can still be made by those skilled at the field related with the present invention and do not depart from the spirits of the present invention, so they should be regarded to fall into the scope defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 101121120 A | Jun 2012 | TW | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6737684 | Takagi et al. | May 2004 | B1 |
| 7242038 | Oda et al. | Jul 2007 | B2 |
| 7656002 | Barratt et al. | Feb 2010 | B1 |
| 7718486 | Krutko et al. | May 2010 | B2 |
| 20020121647 | Taylor | Sep 2002 | A1 |
| 20040082091 | Taylor et al. | Apr 2004 | A1 |
| 20050139863 | Welser et al. | Jun 2005 | A1 |
| 20060141682 | Taylor et al. | Jun 2006 | A1 |
| 20070278523 | Lin et al. | Dec 2007 | A1 |
| 20080023725 | Cooke et al. | Jan 2008 | A1 |
| 20120104462 | Ichikawa | May 2012 | A1 |
| 20120175681 | Stevens et al. | Jul 2012 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20130334564 A1 | Dec 2013 | US |
