Claims
- 1. A metal oxide semiconductor (MOS) field effect transistor configuration, comprising:
a semiconductor body; a semiconductor pillar pointing away from said semiconductor body and forming a body region, said body region connected to said semiconductor body and due to said semiconductor body, said body region being at a fixed potential; a filling insulator surrounding said semiconductor pillar and disposed on said semiconductor body; and a source, a drain and a gate embedded between said semiconductor pillar and said filling insulator.
- 2. The MOS field effect transistor configuration according to claim 1:wherein a boundary region between said semiconductor pillar and said filling insulator has trenches formed therein for forming said source and said drain; and further comprising a conductive material filling said trenches, and a source zone and a drain zone are formed by one of diffusion and implantation from said trenches.
- 3. The MOS field effect transistor configuration according to claim 2:wherein said boundary region has an additional trench formed therein between said trenches for said source and said drain; further comprising a gate insulator insulating said additional trench; and further comprising a further conductive material filling said additional trench for forming said gate.
- 4. The MOS transistor configuration according to claim 1, wherein said semiconductor pillar is one of a plurality of pillars having various conductivity types disposed on said semiconductor body for at least one n-channel MOS field effect transistor and a p-channel MOS field effect transistor in a CMOS configuration.
- 5. The MOS field effect transistor configuration according to claim 1, wherein said filling insulator is formed of a material with a low dielectric constant.
- 6. The MOS field effect transistor configuration according to claim 1, wherein said filling insulator is formed of at least one material selected from the group consisting of silicon dioxide, non-doped polycrystalline silicon, and a substance with a low dielectric constant.
- 7. The MOS field effect transistor configuration according to claim 3, wherein said trenches and said additional trench have given depths, and a channel width is determined by said given depths of said trenches and said additional trench.
- 8. The MOS field effect transistor configuration according to claim 1, wherein said semiconductor body and said semiconductor pillar have an equivalent conductivity type and are both one of n-doped and p-doped.
- 9. The MOS field effect transistor configuration according to claim 1, wherein said semiconductor body and said semiconductor pillar are formed of a material selected from the group consisting of silicon, an AIIIBV semiconductor and SiC.
- 10. The MOS field effect transistor configuration according to claim 3, wherein said additional trench for said gate at least touches said trenches for said source and said drain.
- 11. The MOS field effect transistor configuration according to claim 3, wherein said gate insulator is formed of at least one material selected from the group consisting of silicon dioxide and silicon nitride.
- 12. A process for producing a metal oxide semiconductor (MOS) field effect transistor configuration, which comprises the steps of:
providing a semiconductor body; etching an initial semiconductor pillar in the semiconductor body; surrounding the initial semiconductor pillar with a filling insulator; forming trenches for a source, a drain and a gate in a boundary region between the initial semiconductor pillar and the filling insulator, so that, of the initial semiconductor pillar, only a semiconductor pillar forming a body region remains; introducing a dopant of a first conductivity type opposite to a dopant of a second conductivity type of the semiconductor pillar from the trenches for the source and the drain into regions of the semiconductor pillar which adjoin the trenches; filling a trench of the trenches with an insulating layer; and disposing a conductive material on the insulating layer for forming the gate.
- 13. The process according to claim 12, which comprises forming the initial semiconductor pillar to have a shape selected from the group consisting of rectangular shapes, oval shapes, T-shapes and trapezoidal shapes.
Priority Claims (1)
Number |
Date |
Country |
Kind |
100 04 872.2 |
Feb 2000 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of copending International Application No. PCT/DE01/00441, filed Feb. 2, 2001, which designated the United States and was not published in English.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/DE01/00441 |
Feb 2001 |
US |
Child |
10213414 |
Aug 2002 |
US |