Claims
- 1. A high-level supply voltage drop detection circuit comprising: an nMOS transistor whose drain and gate are connected to a high-level supply voltage input terminal at which a high-level supply voltage is applied; a capacitor connected at a first end thereof to the source of the nMOS transistor and connected at a second end thereof to a low-level supply voltage input terminal at which a low-level supply voltage is applied; a pMOS transistor whose source is connected to said first end of said capacitor and whose gate is connected to the high-level supply voltage input terminal; and a resistor connected at one end thereof to the drain of the pMOS transistor and connected at the other end to the low-level supply voltage input terminal, wherein a high-level supply voltage drop detection signal is obtained from the drain of the pMOS transistor.
- 2. A high-level supply voltage drop detection circuit comprising: first and second nMOS transistors whose drain and gate are connected to a high-level supply voltage input terminal at which a high-level supply voltage is applied; a capacitor connected at a first end thereof to the source of the first nMOS transistor and connected at a second end thereof to a low-level supply voltage input terminal at which a low-level supply voltage is applied; a pMOS transistor whose source is connected to said first end of said capacitor and whose gate is connected to the source of the second nMOS transistor; a first resistor connected at one end thereof to the drain of the pMOS transistor and connected at the other end to the low-level supply voltage input terminal; and a second resistor connected at one end thereof to the source of the second nMOS transistor and connected at the other end to the low-level supply voltage input terminal, wherein a high-level supply voltage drop detection signal is obtained from the drain of the pMOS transistor.
- 3. A high-level supply voltage drop detection circuit comprising: first and second nMOS transistors whose drain and gate are connected to a high-level supply voltage input terminal at which a high-level supply voltage is applied; a capacitor connected at a first end thereof to the source of the first nMOS transistor and connected at a second end thereof to a low-level supply voltage input terminal at which a low-level supply voltage is applied; a pMOS transistor whose source is connected to said first end of said capacitor and whose gate is connected to the source of the second nMOS transistor; a first resistor connected at one end thereof to the drain of the pMOS transistor and connected at the other end to the low-level supply voltage input terminal; a second resistor connected at one end thereof to the source of the second nMOS transistor and connected at the other end to the low-level supply voltage input terminal; and a second capacitor connected at one end thereof to the high-level supply voltage input terminal and connected at the other end to the gate of the pMOS transistor, wherein a high-level supply voltage drop detection signal is obtained from the drain of the pMOS transistor.
Priority Claims (4)
Number |
Date |
Country |
Kind |
4-243136 |
Sep 1992 |
JPX |
|
4-246598 |
Sep 1992 |
JPX |
|
4-248309 |
Sep 1992 |
JPX |
|
4-248310 |
Sep 1992 |
JPX |
|
Parent Case Info
This is a continuation of application Ser. No. 08/353,312 filed Dec. 5, 1994 now abandoned, which is a continuation of Ser. No. 08/113,894, filed Aug. 31, 1993, now abandoned.
US Referenced Citations (7)
Foreign Referenced Citations (12)
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Continuations (2)
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Number |
Date |
Country |
Parent |
353312 |
Dec 1994 |
|
Parent |
113894 |
Aug 1993 |
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