Claims
- 1. A metal oxide semiconductor (MOS) field effect transistor configuration, comprising:a semiconductor body; a semiconductor pillar pointing away from said semiconductor body and forming a body region, said body region connected to said semiconductor body and due to said semiconductor body, said body region being at a fixed potential; a filling insulator surrounding said semiconductor pillar and disposed on said semiconductor body; a sources a drain and a gate embedded between said semiconductor pillar and said filling insulator; a boundary region between said semiconductor pillar and said filling insulator having trenches formed therein for forming said source and said drain; and a conductive material filling said trenches wherein a source zone and a drain zone are formed by one of diffusion and implantation from said trenches.
- 2. The MOS field effect transistor configuration according to claim 1:wherein said boundary region has an additional trench formed therein between said trenches for said source and said drain; further comprising a gate insulator insulating said additional trench; and further comprising a further conductive material filling said additional trench for forming said gate.
- 3. The MOS transistor configuration according to claim 1, wherein said semiconductor pillar is one of a plurality of pillars having various conductivity types disposed on said semiconductor body for at least one n-channel MOS field effect transistor and a p-channel MOS field effect transistor in a CMOS configuration.
- 4. The MOS field effect translator configuration according to claim 3, wherein said trenches and said additional trench have given depths, and a channel width is determined by said given depths of said trenches and said additional trench.
- 5. The MOS field effect transistor configuration according to claim 1, wherein said filling insulator is formed of a material with a low dielectric constant.
- 6. The MOS field effect transistor configuration according to claim 2, wherein said gate insulator is formed of at least one material selected from the group consisting of silicon dioxide and silicon nitride.
- 7. The MOS field effect transistor configuration according to claim 1, wherein said filling insulator is formed of at least one material selected from the group consisting of silicon dioxide, non-doped polycrystalline silicon, and a substance with a low dielectric constant.
- 8. The MOS field effect transistor configuration according to claim 1, wherein said semiconductor body and said semiconductor pillar have an equivalent conductivity type and are both one of n-doped and p-doped.
- 9. The MOS field effect transistor configuration according to claim 1, wherein said semiconductor body and said semiconductor pillar are formed of a material selected from the group consisting of silicon, an AIIIBV semiconductor and SiC.
- 10. The MOS field effect transistor configuration according to claim 2, wherein said additional trench for said gate at least touches said trenches for said source and said drain.
Priority Claims (1)
Number |
Date |
Country |
Kind |
100 04 872 |
Feb 2000 |
DE |
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CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of copending International Application No. PCT/DE01/00441, filed Feb. 2, 2001, which designated the United States and was not published in English.
US Referenced Citations (4)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0 472 726 |
Mar 1992 |
EP |
0 510 667 |
Oct 1992 |
EP |
09 283 766 |
Oct 1997 |
JP |
Non-Patent Literature Citations (1)
Entry |
Stephen C. Kuehne et al.: “SOI MOSFET with Buried Body Strap by Wafer Bonding”, IEEE Transactions on Electron Devices, vol. 45, No. 5, May 1998, pp. 1084-1090. |
Continuations (1)
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Number |
Date |
Country |
Parent |
PCT/DE01/00441 |
Feb 2001 |
US |
Child |
10/213414 |
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US |